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| ? cy7c63310, cy7c638xx encore? ii low speed usb peripheral controller cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document 38-08035 rev. *m revised october 29, 2010 features usb 2.0-usb-if certified (tid # 40000085) encore? ii usb - ?enhanced component reduction? ? crystalless oscillator with support for an external clock. the internal oscillator eliminates the need for an external crystal or resonator. ? two internal 3.3 v regulators and an internal usb pull-up resistor ? configurable i/o for real world interface without external components usb specification compliance ? conforms to usb specification, version 2.0 ? conforms to usb hid spec ification, version 1.1 ? supports one low speed usb device address ? supports one control endpoint and two data endpoints ? integrated usb transceiver with dedicated 3.3 v regulator for usb signalling and d? pull-up. enhanced 8-bit microcontroller ? harvard architecture ? m8c cpu speed is up to 24 mhz or sourced by an external clock signal internal memory ? up to 256 bytes of ram ? up to eight kbytes of flash including eerom emulation interface can auto configure to operate as ps/2 or usb ? no external components for switching between ps/2 and usb modes ? no general purpose i/o (gpio) pins required to manage dual mode capability low power consumption ? typically 10 ma at 6 mhz ? 10 ? a sleep in system reprogrammability: ? allows easy firmware update gpio ports ? up to 20 gpio pins ? 2 ma source current on all gpio pins. configurable 8 or ? 50 ma/pin current sink on designated pins. ? each gpio port supports high impedance inputs, configurable pull-up, open drain output, cmos/ttl inputs, and cmos output ? maskable interrupts on all i/o pins a dedicated 3.3 v regulator for the usb phy. aids in signalling and d? line pull-up 125 ma 3.3 v voltage regulator powers external 3.3 v devices 3.3 v i/o pins ? 4 io pins with 3.3 v logic levels ? each 3.3 v pin supports high impedance input, internal pull-up, open drain output or traditional cmos output spi serial communication ? master or slave operation ? configurable up to 4 mbit/sec ond transfers in the master mode ? supports half duplex single data line mode for optical sensors 2-channel 8-bit or 1-channel 16 -bit capture timer registers. capture timer registers store both rising and falling edge times. ? two registers each for two input pins ? separate registers for rising and falling edge capture ? simplifies the interface to rf inputs for wireless applications internal low power wakeup timer during suspend mode: ? periodic wakeup with no external components 12-bit programmable interval timer with interrupts advanced development tools based on cypress psoc? tools watchdog timer (wdt) low-voltage detection with user configurable threshold voltages operating voltage from 4.0 v to 5.5 v dc operating temperature from 0?70 c available in 16 and 18-pin pdip; 16, 18, and 24-pin soic; 24-pin qsop, and 32-pin qfn packages industry standard programmer support 0.1 applications the cy7c63310/cy7c638xx is targeted for the following applications: pc hid devices ? mice (optomechanical, optical, trackball) gaming ? joysticks ? game pad general purpose ? barcode scanners ? pos terminal ? consumer electronics ? to y s ? remote controls ? security dongles [+] feedback
cy7c63310, cy7c638xx document 38-08035 rev. *m page 2 of 86 contents introduction ....................................................................... 4 conventions ...................................................................... 4 pinouts .............................................................................. 5 cpu architecture .............................................................. 8 cpu registers ................................................................... 9 instruction set summary ............................................... 13 memory organization ..................................................... 14 clocking .......................................................................... 20 reset ................................................................................ 28 sleep mode ...................................................................... 29 low voltage detect control .......................................... 32 general purpose i/o (gpio) ports ................................ 34 serial peripheral interface (spi) .................................... 41 timer registers .............................................................. 44 interrupt controller ......................................................... 51 regulator output ............................................................ 57 usb/ps2 transceiver ..................................................... 58 usb transceiver configuration .................................... 58 usb serial interface engine (s ie) ........ .............. ........... 58 usb device ..................................................................... 59 usb mode tables ........................................................... 62 register summary .......................................................... 65 voltage vs cpu frequency characteristics ................ 68 absolute maximum ratings .......................................... 69 dc characteristics ......................................................... 69 ac characteristics ......................................................... 70 ordering information ...................................................... 76 package handling ........................................................... 76 acronyms ........................................................................ 82 document conventions .................................................. 82 document history page ................................................. 83 sales, solutions, and legal information ...................... 86 [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 3 of 86 internal 24 mhz oscillator 3.3v regulator clock control por / low-voltage detect watchdog timer ram up to 256 byte m8c cpu flash up to 8k byte up to 14 extended io pins low-speed usb/ps2 transceiver and pull up up to 6 gpio pins wakeup timer 16-bit free running timer 12-bit timer 4 3vio/spi pins vdd interrupt control low-speed usb sie external clock logic block diagram [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 4 of 86 3. introduction cypress has reinvented its leadership position in the low speed usb market with a new family of innovative microcontrollers. introducing encore ii usb - ?enhanced component reduction.? cypress has leveraged its design expertise in usb solutions to advance its family of low speed usb microcontrollers, which enable peripheral developers to design new products with a minimum number of components. the encore ii usb technology builds on the encore family. the encore family has an integrated oscillator that elim inates the external crystal or resonator, reducing overall cost. also integrated into this chip are other external components commonly found in low speed usb applications, such as pull-up resistors, wakeup circuitry, and a 3.3v regulator. integrating these components reduces the overall system cost. the encore ii is an 8-bit flash programmable microcontroller with an integrated low speed usb interface. the instruction set is optimized specifically for usb and ps/2 operations, although the microcontrollers may be used for a variety of other embedded applications. the encore ii features up to 20 gpio pins to support usb, ps/2, and other applications. the io pins are grouped into four ports (port 0 to 3). the pins on port 0 and port 1 may each be configured individually while the pins on ports 2 and 3 are configured only as a group. each gpio port supports high impedance inputs, configurable pull-up, open drain output, cmos/ttl inputs, and cmos output with up to five pins that support a programmable drive strength of up to 50 ma sink current. gpio port 1 features four pins that interface at a voltage level of 3.3v. additionally, each io pin may be used to generate a gpio interrupt to the microcontr oller. each gpio port has its own gpio interrupt vector; in a ddition, gpio port 0 has three dedicated pins that have independent interrupt vectors (p0.2 - p0.4). the encore ii features an internal oscillator. with the presence of usb traffic, the internal oscillator may be set to precisely tune to usb timing requirements (24 mhz 1.5%). optionally, an external 12 mhz or 24 mhz clock is used to provide a higher precision reference for usb operation. the clock generator provides the 12 mhz and 24 mhz cl ocks that remain internal to the microcontroller. the encore ii also has a 12-bit program - mable interval timer and a 16-bit free running timer with capture timer registers. in addit ion, the encore ii includes a watchdog timer and a vectored interrupt controller. the encore ii has up to eight kbytes of flash for user code and up to 256 bytes of ram for stack space and user variables. the power on reset circuit detects logic when power is applied to the device, resets the logic to a known state, and begins executing instructions at flash address 0x0000. when power falls below a programmable trip voltage, it generates a reset or may be configured to generate an interrupt. there is a low voltage detect circuit that detects when v cc drops below a programmable trip voltage. it is configurable to generate an lvd interrupt to inform the processo r about the low voltage event. por and lvd share the same interrupt. there is no separate interrupt for each. the watchdog timer may be used to ensure the firmware never gets stalled in an infinite loop. the microcontroller supports 22 maskable interrupts in the vectored interrupt controller. interrupt sources include a usb bus reset, lvr/por, a programmable interval timer, a 1.024 ms output from the free-running timer, three usb endpoints, two capture timers, four gpio ports, three port 0 pins, two spi, a 16-bit free running timer wrap, an internal sleep timer, and a bus active interrupt. the sleep timer causes periodic interrupts when enabled. the usb endpoints interrupt after a usb transaction complete is on the bus. the capture timers interrupt when a new timer value is saved because of a selected gpio edge event. a total of seven gpio interrupts support both ttl or cmos thresholds. for additional flexibility on the edge sensitive gpio pins, the interrupt polarity is programmed as rising or falling. the free-running 16-bit timer provid es two interrupt sources: the 1.024 ms outputs and the free running counter wrap interrupt. the programmable interval timer provides up to 1 ?? sec resolution and provides an interrupt every time it expires. these timers are used to measure the duration of an event under firmware control by reading the desi red timer at the start and at the end of an event, then calculating the difference between the two values. the two 8-bit capture timer registers save a programmable 8-bit range of the free-running timer when a gpio edge occurs on the two capture pins (p0.5, p0.6). the two 8-bit captures may be ganged into a single 16-bit capture. the encore ii includes an integrated usb serial interface engine (sie) that allows the chip to easily interface to a usb host. the hardware supports one usb device address with three endpoints. the usb d+ and d? pins are optionally used as ps/2 sclk and sdata signals so that products are designed to respond to either usb or ps/2 modes of o peration. the ps/2 operation is supported with internal 5 k ? pull-up resistors on p1.0 (d+) and p1.1 (d?), and an interrupt to signal the start of ps/2 activity. in usb mode, the in tegrated 1.5 k ?? pull-up resistor on d? may be controlled under firmware. no external components are necessary for dual usb and ps/2 systems, and no gpio pins need to be dedicated to switching between modes. the encore ii supports in system programming by using the d+ and d? pins as the serial programming mode interface. the programming protocol is not usb. 4. conventions in this data sheet, bit positions in the registers are shaded to indicate which members of the en core ii family implement the bits. available in all encore ii family members cy7c638(1/2/3)3 only [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 5 of 86 5. pinouts figure 5-1. pin diagrams 1 2 3 4 5 6 9 11 15 16 17 18 19 20 22 21 nc p0.7 tio1/p0.6 tio0/p0.5 int2/p0.4 int1/p0.3 p0.0 p2.0 p1.5/smosi p1.3/ssel p3.1 p3.0 v cc p1.2/vreg p1.1/d? p1.0/d+ 14 p1.4/sclk 10 p2.1 nc v ss 12 13 7 8 int0/p0.2 p0.1 24 23 p1.7 p1.6/smiso 24-pin qsop cy7c63823 1 2 3 4 6 7 8 10 11 12 13 15 16 18 17 ssel/p1.3 sclk/p1.4 smosi/p1.5 smiso/p1.6 p0.7 tio0/p0.5 p1.2/vreg p1.1/d? p1.0/d+ p0.0 p0.1 p0.2/int0 18-pin pdip v cc 9 tio1/p0.6 int2/p0.4 p0.3/int1 cy7c63813 5 14 p1.7 v ss 1 2 3 4 6 7 8 9 10 11 13 14 16 15 ssel/p1.3 sclk/p1.4 smosi/p1.5 smiso/p1.6 tio0/p0.5 int1/p0.3 p1.2 p1.1/d? p1.0/d+ p0.1 p0.2/int0 p0.0 16-pin pdip v cc int2/p0.4 5 12 tio1/p0.6 v ss top view cy7c63801, cy7c63310 1 2 3 4 6 7 8 9 10 11 13 14 16 15 tio1/p0.6 tio0/p0.5 int2/p0.4 int1/p0.3 p0.1 v ss p1.6/smiso p1.4/sclk p1.3/ssel p1.1/d? p1.0/d+ v cc 16-pin soic p1.5/smosi p0.0 5 12 int0/p0.2 p1.2 cy7c63801, cy7c63310 1 2 3 4 6 7 8 10 11 12 13 15 16 18 17 p0.7 tio1/p0.6 tio0/p0.5 int2/p0.4 int0/p0.2 p0.0 p1.7 p1.5/smosi p1.4/sclk p1.2/vreg v cc p1.1/d? 18-pin soic p1.6/smiso 9 p0.1 v ss p1.0/d+ cy7c63813 5 14 int1/p0.3 p1.3/ssel 1 2 3 4 5 6 9 11 15 16 17 18 19 20 22 21 nc p0.7 tio1/p0.6 tio0/p0.5 int2/p0.4 int1/p0.3 p0.0 p2.0 p1.6/smiso p3.0 p1.4/sclk p3.1 p1.2/vreg p1.3/ssel v cc p1.1/d? 14 p1.5/smosi 10 p2.1 v ss p1.0/d+ 12 13 7 8 int0/p0.2 p0.1 24 23 nc p1.7 24-pin soic cy7c63823 1 2 3 4 6 7 8 9 10 11 13 14 16 15 tio1/p0.6 tio0/p0.5 int2/p0.4 int1/p0.3 p0.1 v ss p1.6/smiso p1.4/sclk p1.3/ssel p1.1/d? p1.0/d+ v cc p1.5/smosi p0.0 5 12 int0/p0.2 p1.2/vreg cy7c63803 16-pin soic 1 2 3 4 5 6 21 19 23 25 22 26 20 24 18 9 8 12 13 10 14 16 11 17 15 7 27 28 32 30 29 31 p0.6/tio1 p0.5/tio0 p0.4/int2 p0.3/int1 p0.2/int0 p0.1 p0.0 p2.1 p2.0 nc nc nc vss p1.0/d+ p1.1/d- vdd nc nc p1.3/ssel p3.0 p3.1 p1.4/sclk p1.5/smosi p1.6/miso p1.7 p0.7 nc nc nc nc nc p1.2/vreg 1 2 3 4 5 6 21 19 23 25 22 26 20 24 18 9 8 12 13 10 14 16 11 17 15 7 27 28 32 30 29 31 p0.6/tio1 p0.5/tio0 p0.4/int2 p0.3/int1 p0.2/int0 p0.1 p0.0 p2.1 p2.0 nc nc nc vss p1.0/d+ p1.1/d- vdd nc nc p1.3/ssel p3.0 p3.1 p1.4/sclk p1.5/smosi p1.6/miso p1.7 p0.7 nc nc nc nc nc p1.2/vreg 32-pin qfn cy7c63833 cy7c63833 32-pin sawn qfn [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 6 of 86 figure 5-2. cy7c63823 die form die step = 1792.98 m x 2272.998 m die size = 1727 m x 2187 m bond pad opening = 70 m x 70 m die thickness = 14 mils legend 1 2 4 3 5 6 8 7 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 cypress logo x y table 5-1. die pad summary pad number pad name x (microns) y (microns) 1 p0.7 ?742.730 911.990 2 p0.6 ?755.060 792.200 3 p0.5 ?755.060 699.300 4 p0.4 ?755.060 606.400 5 p0.3 ?755.060 ?430.080 6 p0.2 ?755.060 ?522.980 7 p0.1 ?755.060 ?618.830 8 p0.0 clkin ?755.060 ?714.020 9 p2.1 ?755.060 ?810.220 10 p2.0 ?393.580 ?977.930 11 vss 537.500 ?964.700 12 pi.0 d+ 736.110 ?936.680 13 p1.1 d? 736.110 ?625.130 14 vdd 736.110 ?260.670 15 p1.2 vreg 736.110 53.800 16 p1.3 723.510 336.780 17 p3.0 723.510 438.690 18 p3.1 723.510 532.880 19 p1.4 723.510 635.310 20 p1.5 smosi 723.510 728.220 21 p1.6 smiso 723.510 839.290 22 p1.7 696.630 1008.480 23 reserved ?795.400 1023.270 [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 7 of 86 table 5-2. pin description 32 qfn 24 qsop 24 soic 18 sioc 18 pdip 16 soic 16 pdip name description 21 19 18 ? ? ? ? p3.0 gpio port 3 . configured as a group (byte). 22 20 19 ? ? ? ? p3.1 9 11 11 ? ? ? ? p2.0 gpio port 2 . configured as a group (byte). 8 10 10 ? ? ? ? p2.1 14 14 13 10 15 9 13 p1.0/d+ gpio port 1 bit 0/usb d+ [1] if this pin is used as a general purpose output, it draws current. this pin must be configured as an input to reduce current draw. 15 15 14 11 16 10 14 p1.1/d? gpio port 1 bit 1/usb d? [1] if this pin is used as a general purpose output, it draws current. this pin must be configured as an input to reduce current draw. 18 17 16 13 18 12 16 p1.2/vreg gpio port 1 bit 2 . configured individually. ? 3.3v if regulator is enabled. (the 3.3 v regulator is not available in the cy7c63310 and cy7c63801.) a 1- ? f min, 2- ? f max capacitor is required on vreg output. 20 18 17 14 1 13 1 p1.3/ssel gpio port 1 bit 3 . configured individually. ? alternate function is ssel signal of the spi bus ttl voltage thresholds. although vreg is not available with the cy7c63310, 3.3 v i/o is still available. 23 21 20 15 2 14 2 p1.4/sclk gpio port 1 bit 4 . configured individually. ? alternate function is sclk signal of the spi bus ttl voltage thresholds. although vreg is not available with the cy7c63310, 3.3 v i/o is still available. 24 22 21 16 3 15 3 p1.5/smosi gpio port 1 bit 5 . configured individually. ? alternate function is smosi signal of the spi bus ttl voltage thresholds. although vreg is not available with the cy7c63310, 3.3 v i/o is still available. 25 23 22 17 4 16 4 p1.6/smiso gpio port 1 bit 6 . configured individually. ? alternate function is smiso signal of the spi bus ttl voltage thresholds. although vreg is not available with the cy7c63310, 3.3 v i/o is still available. 26 24 23 18 5 ? ? p1.7 gpio port 1 bit 7 . configured individually. ttl voltage threshold. 7 9 9 8 13 7 11 p0.0 gpio port 0 bit 0 . configured individually. on cy7c638xx and cy7c63310, external clock input when configured as clock in. 6 8 8 7 12 6 10 p0.1 gpio port 0 bit 1 . configured individually. on cy7c638xx and cy7c63310, clock output when configured as clock out. 5 7 7 6 11 5 9 p0.2/int0 gpio port 0 bit 2 . configured individually. ? optional rising edge interrupt int0. 4 6 6 5 10 4 8 p0.3/int1 gpio port 0 bit 3 . configured individually. ? optional rising edge interrupt int1. 3 5 5 4 9 3 7 p0.4/int2 gpio port 0 bit 4 . configured individually. ? optional rising edge interrupt int2. note 1. p1.0(d+) and p1.1(d?) pins must be in i/o mode when used as gpio and in i sb mode. [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 8 of 86 6. cpu architecture this family of microcontrollers is based on a high performance, 8-bit, harvard architecture microprocessor. five registers control the primary operation of the cpu core. these registers are affected by various instructions, but are not directly accessible through the register space by the user. the 16-bit program counter register (cpu_pc) allows direct addressing of the full 8 kbyt es of program memory space. the accumulator register (cpu_a) is the general purpose register, which holds the results of instructions that specify any of the source addressing modes. the index register (cpu_x) hold s an offset value that is used in the indexed addressing modes. typically, this is used to address a block of data within the data memory space. the stack pointer register (cpu _sp) holds the address of the current top of the stack in the data memory space. it is affected by the push, pop, lcall, call, reti, and ret instructions, which manage the software stack. it is also affected by the swap and add instructions. the flag register (cpu_f) has three status bits: zero flag bit [1]; carry flag bit [2]; supervisory state bit [3]. the global interrupt enable bit [0] globally enables or disables interrupts. the user cannot manipulate the s upervisory state status bit [3]. the flags are affected by arithmetic, logic, and shift operations. the manner in which each flag is changed is dependent upon the instruction being executed, such as and, or, xor, and others. see table 8-1 on page 13 . 2 4 4 3 8 2 6 p0.5/tio0 gpio port 0 bit 5 . configured individually ? alternate function timer capture inputs or timer output tio0 1 3 3 2 7 1 5 p0.6/tio1 gpio port 0 bit 6 . configured individually ? alternate function timer capture inputs or timer output tio1 32 2 2 1 6 ? ? p0.7 gpio port 0 bit 7 . configured individually ? not present in the 16 pin pdip or soic package 10 1 1 ? ? ? ? nc no connect 11 12 24 ? ? ? ? nc no connect 12 ? ? ? ? ? ? nc no connect 17 ? ? ? ? ? ? nc no connect 19 ? ? ? ? ? ? nc no connect 27 ? ? ? ? ? ? nc no connect 28 ? ? ? ? ? ? nc no connect 29 ? ? ? ? ? ? nc no connect 30 ? ? ? ? ? ? nc no connect 31 ? ? ? ? ? ? nc no connect 16 16 15 12 17 11 15 vcc supply 13 13 12 9 14 8 12 v ss ground table 5-2. pin description (continued) 32 qfn 24 qsop 24 soic 18 sioc 18 pdip 16 soic 16 pdip name description table 6-1. cpu registers and register names cpu register register name flags cpu_f program counter cpu_pc accumulator cpu_a stack pointer cpu_sp index cpu_x [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 9 of 86 7. cpu registers the cpu registers in encore ii devices are in two banks with 256 registers in each ban k. bit[4]/xi/o bit in the cpu flags regis ter must be set/cleared to select between the two register banks table 7-1 on page 9 7.1 flags register the flags register is set or reset only with logical instruction. table 7-1. cpu flags register (cpu_f) [r/w] bit # 7 6 5 4 3 2 1 0 field reserved xio super carry zero global ie read/write ? ? ? r/w r rw rw rw default 0 0 0 0 0 0 1 0 bit [7:5]: reserved bit 4: xio set by the user to select between the register banks 0 = bank 0 1 = bank 1 bit 3: super indicates whether the cpu is executing us er code or supervisor code. (this code cannot be accessed directly by the user.) 0 = user code 1 = supervisor code bit 2: carry set by the cpu to indicate whether there has been a carry in the previous l ogical/arithmetic operation. 0 = no carry 1 = carry bit 1: zero set by the cpu to indicate whether there has been a zero result in the previous logical/arithmetic operation. 0 = not equal to zero 1 = equal to zero bit 0: global ie determines whether all interrupts are enabled or disabled 0 = disabled 1 = enabled note cpu_f register is only readable with th e explicit register address 0xf7. the or f, expr and and f, expr instructions must be used to set and clear the cpu_f bits. table 7-2. cpu accumulator register (cpu_a) bit # 7 6 5 4 3 2 1 0 field cpu accumulator [7:0] read/write ? ? ? ? ? ? ? ? default 0 0 0 0 0 0 0 0 bit [7:0]: cpu accumulator [7:0] 8-bit data value holds the result of any logical/arithmetic in struction that uses a source addressing mode [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 10 of 86 7.2 addressing modes 7.2.1 source immediate the result of an instruction usin g this addressing mode is placed in the a register, the f register, the sp register, or the x register, which is specified as part of the instruction opcode. operand 1 is an immediate value that serves as a source for the instruction. arithmetic instructions require tw o sources; the se cond source is the a or the x register specified in the opcode. instructions using this addressing mode are two bytes in length. examples table 7-3. cpu x register (cpu_x) bit # 7 6 5 4 3 2 1 0 field x [7:0] read/write ? ? ? ? ? ? ? ? default 0 0 0 0 0 0 0 0 bit [7:0]: x [7:0] 8-bit data value holds an index for any instruction that uses an indexed addressing mode. table 7-4. cpu stack pointer register (cpu_sp) bit # 7 6 5 4 3 2 1 0 field stack pointer [7:0] read/write ? ? ? ? ? ? ? ? default 0 0 0 0 0 0 0 0 bit [7:0]: stack pointer [7:0] 8-bit data value holds a pointer to the current top of the stack. table 7-5. cpu program coun ter high register (cpu_pch) bit # 7 6 5 4 3 2 1 0 field program counter [15:8] read/write ? ? ? ? ? ? ? ? default 0 0 0 0 0 0 0 0 bit [7:0]: program counter [15:8] 8-bit data value holds the higher byte of the program counter. table 7-6. cpu program counter low register (cpu_pcl) bit # 7 6 5 4 3 2 1 0 field program counter [7:0] read/write ? ? ? ? ? ? ? ? default 0 0 0 0 0 0 0 0 bit [7:0]: program counter [7:0] 8-bit data value holds the lower byte of the program counter. table 7-7. source immediate opcode operand 1 instruction immediate value add a 7 the immediate value of 7 is added with the accumulator and the result is placed in the accumulator. mov x 8 the immediate value of 8 is moved to the x register. and f 9 the immediate value of 9 is logically anded with the f register and the result is placed in the f register. [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 11 of 86 7.2.2 source direct the result of an instruction usin g this addressing mode is placed in either the a register or the x register, whic h is specified as part of the instruction opc ode. operand 1 is an address that points to a location in the ram memory space or the register space that is the source of the instruction. arithmetic instructions require two sources; the second source is the a register or x register specified in the opcode. instructions using this addressing mode are two bytes in length. examples 7.2.3 source indexed the result of an instruction usin g this addressing mode is placed in either the a register or the x register, whic h is specified as part of the instruction opcode. operand 1 is added to the x register forming an address that points to a location in the ram memory space or the register space that is the source of the instruction. arithmetic instructions require tw o sources; the se cond source is the a register or x register spec ified in the opcod e. instructions using this addressing mode are two bytes in length. examples 7.2.4 destination direct the result of an instruction usin g this addressing mode is placed within the ram memory space or the register space. operand 1 is an address that points to the location of the result. the source for the instruction is either the a register or the x register, which is specified as part of the inst ruction opcode. arithmetic instruc - tions require two sources; the second source is the location specified by operand 1. instructi ons using this addressing mode are two bytes in length. examples 7.2.5 destination indexed the result of an instruction usin g this addressing mode is placed within the ram memory space or the register space. operand 1 is added to the x register forming the address that points to the location of the result. the source for the instruction is the a register. arithmetic in structions require two sources; the second source is the location specified by operand 1 added with the x register. instructions using this addressing mode are two bytes in length. example table 7-8. source direct opcode operand 1 instruction source address add a [7] the value in the ram memory location at address 7 is added with the accumulator, and the result is placed in the accumu- lator. mov x reg[8] the value in the register space at address 8 is moved to the x register. table 7-9. source indexed opcode operand 1 instruction source index add a [x+7] the value in the memory location at address x + 7 is added with the accumulator, and the result is placed in the accumulator. mov x reg[x+8] the value in the register space at address x + 8 is moved to the x register. table 7-10. destination direct opcode operand 1 instruction destination address add [7] a the value in the memory location at address 7 is added with the accumu- lator, and the result is placed in the memory location at address 7. the accumulator is unchanged. mov reg[8] a the accumulator is moved to the register space location at address 8. the accumulator is unchanged. table 7-11. destination indexed opcode operand 1 instruction destination index add [x+7] a the value in the; memory location at address x+7 is added with the accumu- lator, and the result is placed in the memory location at address x+7. the accumulator is unchanged. [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 12 of 86 7.2.6 destination direct source immediate the result of an instruction usin g this addressing mode is placed within the ram memory space or the register space. operand 1 is the address of the result. the source of the instruction is operand 2, which is an immediate value. arithmetic instructions require two sources; the second source is the location specified by operand 1. instructions using this addressing mode are three bytes in length. examples 7.2.7 destination indexed source immediate the result of an instruction usin g this addressing mode is placed within the ram memory space or the register space. operand 1 is added to the x register to form the address of the result. the source of the instruction is o perand 2, which is an immediate value. arithmetic in structions require two sources; the second source is the location specified by operand 1 added with the x register. instructions using this addressing mode are three bytes in length. examples 7.2.8 destination direct source direct the result of an instruction usin g this addressing mode is placed within the ram memory. operand 1 is the address of the result. operand 2 is an address that points to a location in the ram memory that is the source for th e instruction. this addressing mode is only valid on the mov in struction. the instruction using this addressing mode is three bytes in length. . example 7.2.9 source indirect post increment the result of an instruction usin g this addressing mode is placed in the accumulator. operand 1 is an address pointing to a location within the memory space, which contains an address (the indirect address) for the so urce of the instruction. the indirect address is incremented as part of the instruction execution. this addressing mode is only valid on the mvi instruction. the instruction using this addressing mode is two bytes in length. refer to the psoc designer: assembly language user guide for further details on mvi instruction. example 7.2.10 destination indirect post increment the result of an instruction usin g this addressing mode is placed within the memory space. operand 1 is an address pointing to a location within the memory space, which contains an address (the indirect address) for the dest ination of the instruction. the indirect address is incremented as part of the instruction execution. the source for the instruction is the accumulator. this addressing mode is only valid on the mvi instruction. the instruction using this addressing mode is two bytes in length. example table 7-12. destination direct source immediate opcode operand 1 operand 2 instruction destination address immediate value add [7] 5 the value in the memory location at address 7 is added to the immediate value of 5, and the result is placed in the memory location at address 7. mov reg[8] 6 the immediate value of 6 is moved into the register space location at address 8. table 7-13. destination indexed source immediate opcode operand 1 operand 2 instruction destination index immediate value add [x+7] 5 the value in the memory location at address x+7 is added with the immediate value of 5, and the result is placed in the memory location at address x+7. mov reg[x+8] 6 the immediate value of 6 is moved into the location in the register space at address x+8. table 7-14. destination direct source direct opcode operand 1 operand 2 instruction destination address source address mov [7] [8] the value in the memory location at address 8 is moved to the memory location at address 7. table 7-15. source indirect post increment opcode operand 1 instruction source address address mvi a [8] the value in the memory location at address 8 is an indirect address. the memory location pointed to by the indirect address is moved into the accumulator. the indirect address is then incremented. table 7-16. destination indirect post increment opcode operand 1 instruction destination address address mvi [8] a the value in the memory location at address 8 is an indirect address. the accumulator is moved into the memory location pointed to by the indirect address. the indirect address is then incremented. notes 2. interrupt routines take 13 cycles before execution resumes at interrupt vector table. 3. the number of cycles required by an instruction is increased by one for instructions that span 256 byte boundaries in the fla sh memory space. [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 13 of 86 8. instruction set summary the instruction set is summarized in ta b l e 8-1 numerically and serves as a quick refere nce. if more information is needed, the instruction set summary tables are described in detail in the psoc designer assembly language user guide (available on the cypress web site at http://www.cypress.com ). table 8-1. instruction set summary sorted numerically by opcode order [2, 3] opcode hex cycles bytes instruction format flags opcode hex cycles bytes instruction format flags opcode hex cycles bytes instruction format flags 00 15 1 ssc ? 2d 8 2 or [x+expr], a z 5a 5 2 mov [expr], x ? 01 4 2 add a, expr c, z 2e 9 3 or [expr], expr z 5b 4 1 mov a, x z 02 6 2 add a, [expr] c, z 2f 10 3 or [x+expr], expr z 5c 4 1 mov x, a ? 03 7 2 add a, [x+expr] c, z 30 9 1 halt ? 5d 6 2 mov a, reg[expr] z 04 7 2 add [expr], a c, z 31 4 2 xor a, expr z 5e 7 2 mov a, reg[x+expr] z 05 8 2 add [x+expr], a c, z 32 6 2 xor a, [expr] z 5f 10 3 mov [expr], [expr] ? 06 9 3 add [expr], expr c, z 33 7 2 xor a, [x+expr] z 60 5 2 mov reg[expr], a ? 07 10 3 add [x+expr], expr c, z 34 7 2 xor [expr], a z 61 6 2 mov reg[x+expr], a ? 08 4 1 push a ? 35 8 2 xor [x+expr], a z 62 8 3 mov reg[expr], expr ? 09 4 2 adc a, expr c, z 36 9 3 xor [expr], expr z 63 9 3 mov reg[x+expr], expr ? 0a 6 2 adc a, [expr] c, z 37 10 3 xor [x+expr], expr z 64 4 1 asl a c, z 0b 7 2 adc a, [x+expr] c, z 38 5 2 add sp, expr ? 65 7 2 asl [expr] c, z 0c 7 2 adc [expr], a c, z 39 5 2 cmp a, expr if (a=b) z=1 if (a cy7c63310, cy7c638xx document 38-08035 rev. *m page 15 of 86 9.2 data memory organization the cy7c63310/638xx microcontrollers prov ide up to 256 bytes of data ram. 9.3 flash this section describes the flash block of the encore ii. much of the user visible flash functionality including programming and security are implemented in the m8c supervisory read only memory (srom). the encore ii flash has an endurance of 1000 cycles and a 10 year data retention capability. 9.3.1 flash programming and security all flash programming is performed by code in the srom. the registers that contro l the flash programming are only visible to the m8c cpu when it executes out of srom. this makes it impossible to read, write or er ase the flash by bypassing the security mechanisms implemented in the srom. customer firmware can program the flash only through srom calls. the data or code images are sourced through any interface with the appropriate support fi rmware. this type of programming requires a ?boot-loader?, which is a piece of firmware resident on the flash. for safety reasons this boot-loader must not be overwritten during firmware rewrites. the flash provides four extra aux iliary rows that are used to hold flash block protection flags, boot time calibration values, configuration tables, and any device values. the routines for accessing these auxiliary rows are documented in the section srom on page 15 section. the auxiliary rows are not affected by the device erase function. 9.3.2 in system programming most designs that include an encore ii part have a usb connector attached to the usb d+ and d? pins on the device. these designs require the ability to program or reprogram a part through the usb d+ and d? pins alone. the encore ii devices enable this type of in system programming by using the d+ and d? pins as the serial programming mode interface. this allows an external controller to enable the encore ii part to enter the serial programming mode, and then use the test queue to issue flash access functions in the srom. the programming protocol is not usb. 9.4 srom the srom holds code that boots the part, calibrates circuitry, and performs flash operations ( table 9-1 on page 15 lists the srom functions). the functions of the srom are accessed in the normal user code or operatin g from flash. the srom exists in a separate memory space from the user code. the srom functions are accessed by executing the supervisory system call instruction (ssc), which has an opcode of 00h. before executing the ssc the m8c?s accumulator must be loaded with the desired srom function code from table 9-1 on page 15 . undefined functions cause a halt if called from the user code. the srom functions are executing code with calls; as a result, the functions require stack space. with the exception of reset, all of the srom functions have a parameter block in sram that must be configured before executing the ssc. table 9-2 on page 16 lists all possible parameter block variables. the meaning of each parameter, with regards to a specific srom function, is described later in this section. figure 9-2. data memory organization after reset address 8-bit psp 0x00 stack begins here and grows upward. top of ram memory 0xff table 9-1. srom function codes function code function name stack space 00h swbootreset 0 01h readblock 7 02h writeblock 10 03h eraseblock 9 05h eraseall 11 06h tableread 3 07h checksum 3 [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 16 of 86 two important variables that are used for all functions are key1 and key2. these variables are used to help discriminate between valid sscs an d inadvertent sscs. key1 must always have a value of 3 ah, while key2 must have the same value as the stack pointer when the srom function begins execution. this would be the stack pointer value when the ssc opcode is executed, plus three. if either of the keys do not match the expected values, the m8c halts (with the exception of the swbootreset function). the following code puts the correct value in key1 and key2. the code st arts with a halt, to force the program to jump directly into the setup code and not run into it. halt sscop: mov [key1], 3ah mov x, sp mov a, x add a, 3 mov [key2], a 9.4.1 return codes the srom also features return codes and lockouts. return codes aid in the determina tion of the success or failure of a particular function. the return co de is stored in key1?s position in the parameter block. the checksum and tableread functions do not have return codes because key1?s position in the parameter block is used to return other data. read, write, and erase operations ma y fail if the target block is read or write protected. block protection levels are set during device programming. the eraseall function overwrites data in addition to leaving the entire user flash in the erase state. the eraseall function loops through the number of flash macr os in the product, executing the following sequence: erase, bulk program all zeros, erase. after all the user space in all the flash macros are erased, a second loop erases and then programs each protection block with zeros. 9.5 srom function descriptions 9.5.1 swbootreset function the srom function, swbootrese t, is the function that is responsible for transitioning the device from a reset state to running user code. the swbootreset function is executed whenever the srom is entered with an m8c accumulator value of 00h: the sram parameter block is not used as an input to the function. this happens by design after a hardware reset, because the m8c's accumulator is reset to 00h or when the user code executes the ssc instruction with an accumulator value of 00h. the swbootreset function is not executed when the ssc instruction is executed with a bad key value and a non-zero function code. an encore ii device executes the halt instruction if a bad value is given for either key1 or key2. the swbootreset function verifies the integrity of the calibration data by way of a 16-bit checksum, before releasing the m8c to run user code. 9.5.2 readblock function the readblock function is used to read 64 contiguous bytes from flash: a block. this function first checks the protection bits and determines if the desired blockid is readable. if the read protection is turned on, the readblock function exits setting the accumulator and key2 back to 00h. key1 has a value of 01h, indica ting a read failure. if read protection is not enabled, the function reads 64 bytes from the flash using a romx instructi on and stores the results in the sram using an mvi instruction. the first of the 64 bytes are stored in the sram at the address indicated by the value of the pointer parameter. when the readblock completes successfully, the accumulator, key1, and key2 all have a value of 00h. table 9-2. srom function parameters variable name sram address key1/counter/return code 0,f8h key2/tmp 0,f9h blockid 0,fah pointer 0,fbh clock 0,fch mode 0,fdh delay 0,feh pcl 0,ffh table 9-3. srom return codes return code description 00h success 01h function not allowed due to level of protection on block. 02h software reset without hardware reset. 03h fatal error, srom halted. table 9-4. readblock parameters name address description key1 0,f8h 3ah key2 0,f9h stack pointer value, when ssc is ? executed. blockid 0,fah flash block number pointer 0,fbh first of 64 addresses in sram where returned data must be stored. [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 17 of 86 9.5.3 writeblock function the writeblock function is used to store data in the flash. data is moved 64 bytes at a time from sram to flash using this function. the writeblock function first checks the protection bits and determines if the desired bl ockid is writable. if write protection is turned on, the writ eblock function exits setting the accumulator and key2 back to 00h. key1 has a value of 01h, indicating a write failure. the configuration of the writeblock function is straightforward. the blockid of the flash block, where the data is stored, must be determined and stored at sram address fah. the sram address of the first of the 64 bytes to be stored in flash must be indicated using the pointer variable in the parameter block (sram address fbh). finally, the clock and delay value must be set correctly. the clock value deter - mines the length of the write puls e that is used to store the data in the flash. the clock and delay values are dependent on the cpu speed and must be set correctly. 9.5.4 eraseblock function the eraseblock function is used to erase a block of 64 contiguous bytes in flash. the eraseblock function first checks the protection bits and determi nes if the desired blockid is writable. if write protection is turned on, the eraseblock function exits setting the accumulator and key2 back to 00h. key1 has a value of 01h, indicating a write failure. the eraseblock function is only useful as the first step in programming. when a block is erased, the data in the block is not one hundred percent unreadable. if the objective is to obliterate data in a block, the best method is to perform an eraseblock followed by a write - block of all zeros. to set up the parameter block for the eraseblock function, correct key values must be stor ed in key1 and key2. the block number to be erased must be st ored in the blockid variable and the clock and delay values must be set based on the current cpu speed. 9.5.5 protectblock function the encore ii devices offer flash protection on a block by block basis. ta b l e 9-7 lists the protection modes available. in this table, er and ew indicate the ability to perform external reads and writes. for internal writes, iw is used. internal reading is permitted by way of the romx instruction. the ability to read by way of the srom readblock function is indicated by sr. the protection level is stored in two bits according to ta b l e 9-7 . these bits are bit packed into the 64 bytes of the protection block. as a result, each protection block byte stores the protection level for four flash blocks. the bits are packed into a byte, with the lowest numbered bl ock?s protection level stored in the lowest numbered bits ta b l e 9-7 . the first address of the protection block contains the protection level for blocks 0 through 3; the second address is for blocks 4 through 7. the 64th byte stores the protection level for blocks 252 through 255. the level of protection is only decreased by an eraseall, which places zeros in all locations of the protection block. to set the level of protection, the protectb lock function is used. this function takes data from sram, starting at address 80h, and ors it with the current values in the protection block. the result of the or operation is then stor ed in the protection block. the eraseblock function does not change the protection level for a block. because the sram location for the protection data is fixed and there is only one protection block per flash macro, the protectblock function expects very few variables in the parameter block to be set before calling the function. the parameter block values that must be set, besides the keys, are the clock and delay values. table 9-5. writeblock parameters name address description key1 0,f8h 3ah key2 0,f9h stack pointer value, when ssc is executed. blockid 0,fah 8kb flash block number (00h?7fh) ? 4kb flash block number (00h?3fh) 3kb flash block number (00h?2fh) pointer 0,fbh first of 64 addresses in sram, where the data to be stored in flash is located before calling writeblock. clock 0,fch clock divider used to set the write pulse width. delay 0,feh for a cpu speed of 12 mhz set to 56h. table 9-6. eraseblock parameters name address description key1 0,f8h 3ah key2 0,f9h stack pointer value, when ssc is executed. blockid 0,fah flash block number (00h?7fh) clock 0,fch clock divider used to set the erase pulse width. delay 0,feh for a cpu speed of 12 mhz set to 56h table 9-7. protection modes mode settings description marketing 00b sr er ew iw unprotected unprotected 01b sr er ew iw read protect factory upgrade 10b sr er ew iw disable external write field upgrade 11b sr er ew iw disable internal write full protection 7 6 5 4 3 2 1 0 block n+3 block n+2 block n+1 block n [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 18 of 86 9.5.6 eraseall function the eraseall function performs a seri es of steps that destroy the user data in the flash macros and resets the protection block in each flash macro to all zeros (the unprotected state). the eraseall function does not affe ct the three hidden blocks above the protection block, in each flash macro. the first of these four hidden blocks is used to store the protection table for its eight kbytes of user data. the eraseall function begins by erasing the user space of the flash macro with the highest address range. a bulk program of all zeros is then performed on the same flash macro, to destroy all traces of the previous cont ents. the bulk program is followed by a second erase that leaves the flash macro in a state ready for writing. the erase, pr ogram, erase sequence is then performed on the next lowest flash macro in the address space if it exists. after the erase of th e user space, the protection block for the flash macro with the highest address range is erased. following the erase of the protection block, zeros are written into every bit of the protection table. the next lowest flash macro in the address space then has its protection block erased and filled with zeros. the end result of the eraseall func tion is that all user data in the flash is destroyed and the flash is left in an unprogrammed state, ready to accept one of the various write commands. the protection bits for all user data are also reset to the zero state the parameter block values that must be set, besides the keys, are the clock and delay values. 9.5.7 tableread function the tableread function gives the user access to part specific data stored in the flash during manufacturing. it also returns a revision id for the die (not to be confused with the silicon id). the table space for the encore ii is simply a 64 byte row broken up into eight tables of eight bytes. the tables are numbered zero through seven. all user and hidden blocks in the cy7c638xx parts consist of 64 bytes. an internal table (table 0) holds the silicon id and returns the revision id. the silicon id is returned in sram, while the revision and family ids are returned in the cpu_a and cpu_x registers. the silicon id is a value placed in the table by programming the flash and is controlled by cypress semicon - ductor product engineering. the revision id is hard coded into the srom and also redundantly placed in srom table 1. this is discussed in more detail later in this section. srom table 1 holds family/die id and revision id values for the device and returns a one-byte internal revision counter. the internal revision counter starts out with a value of zero and is incremented when one of the other revision numbers is not incre - mented. it is reset to zero when one of the other revision numbers is incremented. the internal revision count is returned in the cpu_a register. the cpu_x register is always set to ffh when table 1 is read. the cpu_a and cpu_x registers always return a value of ffh when t ables 2-7 are read. the blockid value, in the parameter block, indicates which table must be returned to the user. only the three least significant bits of the blockid parameter are used by tableread function for encore ii devices. the upper five bits are ignored. when the function is called, it transfers bytes from the table to sram addresses f8h?ffh. the m8c?s a and x registers are used by the tableread function to return the die?s revi sion id. the revision id is a 16-bit value hard coded into the srom that uniquely identifies the die?s design. the return values for corresponding table calls are tabulated as shown in table 9-11 on page 18 table 9-11. return values for table read table 9-8. protectblock parameters name address description key1 0,f8h 3ah key2 0,f9h stack pointer value when ssc is ? executed. clock 0,fch clock divider used to set the write pulse width. delay 0,feh for a cpu speed of 12 mhz set to 56h. table 9-9. eraseall parameters name address description key1 0,f8h 3ah key2 0,f9h stack pointer value when ssc is ? executed. clock 0,fch clock divider used to set the write pulse width. delay 0,feh for a cpu speed of 12 mhz set to 56h table 9-10. table read parameters name address description key1 0,f8h 3ah key2 0,f9h stack pointer value when ssc is executed. blockid 0,fah table number to read. table number return value a x 0 revision id family id 1 internal revision counter 0xff 2-7 0xff 0xff [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 19 of 86 figure 9-3. srom table the silicon ids for encore ii devices are stored in srom tables in the part, as shown in figure 9-3 the silicon id can be read out from the pa rt using srom table reads (table 0). this is demonstrated in the following pseudo cod e. as mentioned in the section srom on page 15 , the srom variables occupy address f8h through ffh in the sram. each of the variables and their definition is given in the section srom on page 15 . area sscparmblka(ram,abs) org f8h // variables are defined starting at address f8h ssc_key1: ; f8h supervisory key ssc_returncode: blk 1 ; f8h result code ssc_key2 : blk 1 ;f9h supervisory stack ptr key ssc_blockid: blk 1 ; fah block id ssc_pointer: blk 1 ; fbh pointer to data buffer ssc_clock: blk 1 ; fch clock ssc_mode: blk 1 ; fdh clockw clocke multiplier ssc_delay: blk 1 ; feh flash macro sequence delay count ssc_write_resultcode: blk 1 ; ffh temporary result code _main: mov a, 0 mov [ssc_blockid], a// to read from table 0 - silicon id is stored in table 0 //call srom operation to read the srom table mov x, sp ; copy sp into x mov a, x ; a temp stored in x add a, 3 ; create 3 byte stack frame (2 + pushed a) mov [ssc_key2], a ; save stack frame for supervisory code ; load the supervisory code for flash operations mov [ssc_key1], 3ah ;flash_oper_key - 3ah mov a,6 ; load a with specific operation. 06h is the code for table read table 9-1 ssc ; ssc call the supervisory rom // at the end of the ssc command the silicon id is stored in f8 (msb) and f9(lsb) of the sram .terminate: jmp .terminate f8h f9h fah fbh fch fdh feh ffh table 0 table 1 table 2 table 3 table 4 table 5 table 6 table 7 silicon id [15-8] silicon id [7-0] family/ die id revision id [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 20 of 86 9.5.8 checksum function the checksum function calculates a 16-bit checksum over a user specifiable number of blocks, within a single flash macro (bank) starting from block zero. the blockid parameter is used to pass in the number of bl ocks to calculate the checksum over. a blockid value of 1 calculates the checksum of only block 0, while a blockid value of 0 calculates the checksum of all 256 user blocks. the 16-bit checksum is returned in key1 and key2. the parameter key1 holds the lower eight bits of the checksum and the parameter key2 holds the upper eight bits of the checksum. the checksum algorithm executes the followi ng sequence of three instructions over the nu mber of blocks times 64 to be checksummed. romx add [key1], a adc [key2], 0 10. clocking the encore ii has two internal oscillators, the internal 24 mhz oscillator and the 32 khz low power oscillator. the internal 24 mhz oscillator is designed such that it may be trimmed to an output frequency of 24 mhz over temperature and voltage variation. with the presence of usb traffic, the internal 24 mhz oscillator may be set to precisely tune to the usb timing requirements (24 mhz 1.5%). wi thout usb traffic, the internal 24 mhz oscillator accuracy is 24 mhz 5% (between 0?70c). no external components are required to achieve this level of accuracy. the internal low speed oscillator of nominally 32 khz provides a slow clock source for the encore ii in suspend mode, particu - larly to generate a periodic wakeup interrupt and also to provide a clock to sequential logic during power up and power down events when the main clock is stopped. in addition, this oscillator can also be used as a clocking source for the interval timer clock (itmrclk) and capture timer clock (tcapclk). the 32 khz low power oscillator can operate in low power mode or can provide a more accurate clock in normal mode. the internal 32 khz low power oscillator accuracy ranges (between 0?70 c) follow: 5 v normal mode: ?8% to + 16% 5 v lp mode: +12% to + 48% when using the 32 khz oscillator, the pitmrl/h registers must be read until 2 consecutive readin gs match before the result is considered valid. the following firmware example assumes the developer is interested in the lower byte of the pit. read_pit_counter: mov a, reg[pitmrl] mov [57h], a mov a, reg[pitmrl] mov [58h], a mov [59h], a mov a, reg[pitmrl] mov [60h], a ;;;start comparison mov a, [60h] mov x, [59h] sub a, [59h] jz done mov a, [59h] mov x, [58h] sub a, [58h] jz done mov x, [57h] ;;;correct data is in memory location 57h done: mov [57h], x ret table 9-1. checksum parameters name address description key1 0,f8h 3ah key2 0,f9h stack pointer value when ssc is executed. blockid 0,fah number of flash blocks to calculate checksum on. [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 21 of 86 figure 10-1. clock block diagram cpu_clk ext 24 mhz mux clk_usb sel scale clk_24mhz clk_ext cpuclk sel mux scale (divide by 2 n , n = 0-5,7) clk_32 khz lp osc 32 khz sel scale out 0x 12 mhz 0x 12 mhz 1 1 ext/2 11 ext [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 22 of 86 10.1 clock architecture description the encore ii clock selection circuitry allows the selection of independent clocks for the cpu, usb, interval timers and capture timers. the cpu clock cpuclk is sourced from an external clock or the internal 24 mhz oscillator. the selected clock source is optionally divided by 2 n , where n is 0-5,7 (see table 10-4 on page 24 ). usbclk, which must be 12 mhz for the usb sie to function properly, is sourced by the internal 24 mhz oscillator or an external 12 mhz/24 mhz clock. an optional divide by two allows the use of 24 mhz source. the interval timer clock (itmrclk), is sourced from an external clock, the internal 24 mhz oscillator, the internal 32 khz low power oscillator, or from the timer capture clock (tcapclk). a programmable prescaler of 1, 2, 3, 4 then divides the selected source. the timer capture clock (tcapclk) is sourced from an external clock, internal 24 mhz oscillator, or the internal 32 khz low power oscillator. the clkout pin (p0.1) is driven from one of many sources. this is used for test and is also used in some applications. the sources that drive the clkout follow: clkin after the optional eftb filter internal 24 mhz oscillator internal 32 khz low power oscillator cpuclk after the programmable divider table 10-1. iosc trim (iosctr) [0x34] [r/w] bit # 7 6 5 4 3 2 1 0 field foffset[2:0] gain[4:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 d d d d d the iosc calibrate register calibrates the internal oscillator. the reset value is undefined bu t during boot the srom writes a calibration value that is determined during manufacturing test. th is value does not require change during normal use. this is the meaning of ?d? in the default field. bit [7:5]: foffset [2:0] this value is used to trim the frequency of the internal oscillator. these bits are not used in factory calibration and are zer o. setting each of these bits causes the approp riate fine offset in oscillator frequency. foffset bit 0 = 7.5 khz foffset bit 1 = 15 khz foffset bit 2 = 30 khz bit [4:0]: gain [4:0] the effective frequency change of the offset input is controlled through the gain input. a lower value of the gain setting incr eases the gain of the offset input. this value sets the size of ea ch offset step for the internal oscillator. nominal gain change (khz/offsetstep) at each bit, typical conditions (24 mhz operation): gain bit 0 = ?1.5 khz gain bit 1 = ?3.0 khz gain bit 2 = ?6 khz gain bit 3 = ?12 khz gain bit 4 = ?24 khz [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 23 of 86 table 10-2. lposc trim (lposctr) [0x36] [r/w] bit # 7 6 5 4 3 2 1 0 field 32 khz low power reserved 32 khz bias trim [1:0] 32 khz freq trim [3:0] read/write r/w ? r/w r/w r/w r/w r/w r/w default 0 d d d d d d d this register is used to calibrate the 32 khz low speed oscill ator. the reset value is undefined but during boot the srom write s a calibration value that is determined during manufacturing tests. this value does not require change during normal use. this is the meaning of ?d? in the default field. if the 32 khz low power bit is written, care must be taken to not disturb the ? 32 khz bias trim and the 32 khz freq trim fields from their factory calibrated values. bit 7: 32 khz low power 0 = the 32 khz low speed oscillator operates in normal mode 1 = the 32 khz low speed oscillator operates in a low power mode. the oscillator continues to function normally, but with reduced accuracy. bit 6: reserved bit [5:4]: 32 khz bias trim [1:0] these bits control the bias current of the low power oscillator. 0 0 = mid bias 0 1 = high bias 1 0 = reserved 1 1 = reserved note do not program the 32 khz bias trim [1:0] field with the reserved 10b value because the oscillator does not oscillate at all corner conditions with this setting. bit [3:0]: 32 khz freq trim [3:0] these bits are used to trim the frequency of the low power oscillator. table 10-3. cpu/usb clock config ( cpuclkcr) [0x30] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved usb clk/2 disable usb clk select reserved cpuclk select read/write ? r/w r/w ? ? ? ? r/w default 0 0 0 0 0 0 0 0 bit 7: reserved bit 6: usb clk/2 disable this bit only affects the usbclk when the source is the external clock. when the usbclk source is the internal 24 mhz oscillator, the divide by two is always enabled 0 = usbclk source is divided by two. this is the correct sett ing to use when the internal 24 mhz oscillator is used, or when the external source is used with a 24 mhz clock 1 = usbclk is undivided. use this se tting only with a 12 mhz external clock bit 5: usb clk select this bit controls the clo ck source for the usb sie. 0 = internal 24 mhz oscillator. with the presence of usb traffi c, the internal 24 mhz oscillator is trimmed to meet the usb requirement of 1.5% tolerance (see table 10-5 on page 25 ) 1 = external clock?internal oscillato r is not trimmed to usb traffic. proper usb sie operation requires a 12 mhz or 24 mhz clock accurate to <1.5%. bit [4:1]: reserved bit 0: cpu clk select 0 = internal 24 mhz oscillator. 1 = external clock?external clock at clkin (p0.0) pin. note the cpu speed selection is config ured using the osc_cr0 register ( table 10-4 on page 24 ). [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 24 of 86 table 10-4. osc control 0 (osc_cr0) [0x1e0] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved no buzz sleep timer [1:0] cpu speed [2:0] read/write ? ? r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit [7:6]: reserved bit 5: no buzz during sleep (the sleep bit is set in the cpu_scr register? table 11-1 on page 28 ), the lvd and por detection circuit is turned on periodically to detect any por and lvd events on the v cc pin (the sleep duty cycle bits in the eco_tr are used to control the duty cycle? table 13-3 on page 33 ). to facilitate the detection of por and lvd events, the no buzz bit is used to force the lvd and por detection circuit to be continuously enabled during sl eep. this results in a faster response to an lvd or por event during sleep at the expense of a s lightly higher than average sleep current. 0 = the lvd and por detection circuit is turned on periodically as configured in the sleep duty cycle. 1 = the sleep duty cycle value is overridden. the lvd and por detection circuit is always enabled. note the periodic sleep duty cycle enabling is independent with the sleep interval shown in the sleep [1:0] bits below. bit [4:3]: sleep timer [1:0] note sleep intervals are approximate. bit [2:0]: cpu speed [2:0] the encore ii may operate over a range of cpu clock speeds. the reset value for the cpu speed bits is zero; as a result, the default cpu speed is one- eighth of the internal 24 mhz, or 3 mhz regardless of the cpu speed bit?s setting, if the actual cpu speed is greater than 12 mhz, the 24 mhz operating requirements apply. an example of this scenario is a devi ce that is configured to use an external clock, which supplies a frequency of 20 mh z. if the cpu speed register?s value is 0b011, the cpu clock is at 20 mhz. therefore, the supply voltage requirements for the devi ce are the same as if the part were operating at 24 mhz. the operating voltage requirements ar e not relaxed until the cpu speed is at 12 mhz or less . note correct usb operations require the cpu clock speed be at least 1.5 mhz or not less than usb clock/8. if the two clocks have the same source, then the cpu clock divider must not be set to divide by more than 8. if the two clocks have different sources, the maximum ratio of usb clock/ cpu clock must never exceed 8 across the full specification range of both clock sources. note this register exists in the second bank of i/o space. th is requires setting the xio bi t in the cpu flags register. cpu speed [2:0] cpu when internal ? oscillator is selected external clock 000 3 mhz (default) clock in/8 001 6 mhz clock in/4 010 12 mhz clock in/2 011 24 mhz clock in/1 100 1.5 mhz clock in/16 101 750 khz clock in/32 110 187 khz clock in/128 111 reserved reserved [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 25 of 86 table 10-5. usb osclock clock configuration (osclckcr) [0x39] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved fine tune only usb osclock disable read/write ? ? ? ? ? ? r/w r/w default 0 0 0 0 0 0 0 0 this register is used to trim the inter nal 24 mhz oscillator using received low speed usb packets as a timing reference. the usb osclock circuit is active when the internal 24 mhz oscillator provides the usb clock. bit [7:2]: reserved bit 1: fine tune only 0 = fine and course tuning 1 = disable the oscillator lock from perfor ming the coarse-tune portion of its retuni ng. the oscillator lock must be allowed to perform a coarse tuning to tune the oscillato r for correct usb sie operation. after the oscillator is properly tuned, this bit is set to reduce variance in the internal oscillator frequency that would be caused course tuning. bit 0: usb osclock disable 0 = enable. with the presence of usb traffic, the inter nal 24 mhz oscillator precisely tunes to 24 mhz 1.5% 1 = disable. the internal 24 mhz oscillator is not trimmed bas ed on usb packets. this setting is useful when the internal oscillator is not sourcing the usbsie clock. table 10-6. timer clock conf ig (tmrclkcr) [0x31] [r/w] bit # 7 6 5 4 3 2 1 0 field tcapclk divider tcapclk select itmrclk divider itmrclk select read/write r/w r/w r/w r/w r/w r/w r/w r/w default 1 0 0 0 1 1 1 1 bit [7:6]: tcapclk divider [1:0] tcapclk divider controls the tcapclk divisor. 0 0 = divider value 2 0 1 = divider value 4 1 0 = divider value 6 1 1 = divider value 8 bit [5:4]: tcapclk select the tcapclk select field controls the source of the tcapclk. 0 0 = internal 24 mhz oscillator 0 1 = external clock?external clock at clkin (p0.0) input. 1 0 = internal 32 khz low power oscillator 1 1 = tcapclk disabled note the 1024 ? s interval timer is based on the assumption that tcapc lk is running at 4 mhz. changes in tcapclk frequency causes a corresponding change in the 1024 ? s interval timer frequency. bit [3:2]: itmrclk divider itmrclk divider controls the itmrclk divisor. 0 0 = divider value of 1 0 1 = divider value of 2 1 0 = divider value of 3 1 1 = divider value of 4 bit [1:0]: itmrclk select 0 0 = internal 24 mhz oscillator 0 1 = external clock?external clock at clkin (p0.0) input. 1 0 = internal 32 khz low power oscillator 1 1 = tcapclk [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 26 of 86 10.1.1 interval timer clock (itmrclk) the interval timer clock (titmrclk), is sourced from an external clock, the internal 24 mhz oscillator, the internal 32 khz low power oscillator, or the timer capture clock. a programmable prescaler of 1, 2, 3 or 4 then divides the selected source. the 12-bit programmable interval timer is a simple down counter with a programmable reload value. it provides a ? 1 ? s resolution by default. when the down counter reaches zero, the next clock is spent reloading. the reload value is read and written while the counter is runn ing, but the counter must not unintentionally reload when the 12-bit reload value is only partially stored, that is, between the two writes of the 12-bit value. the programmable interval timer generates an interrupt to the cpu on each reload. the parameters to be set show up on the device editor view of psoc designer when the encore ii timer user module is placed. the parameters are pitimer_source and pitimer_divider. the pitimer_sour ce is the clock to the timer and the pitmer_divider is the value the clock is divided by. the interval register (pitmr) holds the value that is loaded into the pit counter on terminal count. the pit counter is a down counter. the programmable interval timer resolution is configurable. for example: tcapclk divide by x of cpu clock (for example, tcapclk divide by 2 of a 24 mhz cpu clock gives a frequency of 12 mhz.) itmrclk divide by x of tcapclk (for example, itmrclk divide by 3 of tcapclk is 4 mhz so resolution is 0.25 ? s.) 10.1.2 timer capture clock (tcapclk) the timer capture clock is sourced from an external clock, internal 24 mhz oscillator or the internal 32 khz low power oscillator. a programmable pre-scaler of 2, 4, 6, or 8 then divides the selected source. figure 10-2. programmable interval timer block diagram system clock clock timer configuration status and control 12-bit reload value 12-bit down counter 12-bit reload counter interrupt c ontroller [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 27 of 86 10.2 cpu clock during sleep mode when the cpu enters sleep mode the cpuclk select (bit [0], table 10-3 on page 23 ) is forced to the internal oscillator, and the oscillator is stopped. when the cpu comes out of sleep mode it r uns on the internal oscillator. the internal oscillator recover y time is three clock cycles of the intern al 32 khz low power oscillator. if the system requires the cpu to run off the external clock af ter awaking from sleep mode, the firmware must switch the clock source for the cpu. figure 10-3. timer capture block diagram 16-bit counter configuration status and control prescale mux capture registers interrupt controller 1ms timer overflow interrupt captimer clock system clock capture0 int capture1 int table 10-1. clock io config (clkiocr) [0x32] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved clkout select read/write ? ? ? - - - r/w r/w default 0 0 0 0 0 0 0 0 bit [7:2]: reserved bit [1:0]: clkout select 0 0 = internal 24 mhz oscillator 0 1 = external clock ? external clock at clkin (p0.0) 1 0 = internal 32 khz low power oscillator 1 1 = cpuclk [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 28 of 86 11. reset the microcontroller supports two types of resets: power on reset (por) and watchdog reset (wdr). when reset is initiated, all registers are restored to their defaul t states and all interrupts are disabled. the occurrence of a reset is recorded in the system status and control register (cpu_scr). bits within this register record the occurrence of por and wdr reset respectively. the firmware interrogates these bits to determine the cause of a reset. the microcontroller resumes execution from flash address 0x0000 after a reset. the internal clocking mode is active after a res et, until changed by the user firmware. note the cpu clock defaults to 3 mhz (internal 24 mhz oscillator divide-by-8 mode) at por to gua rantee operations at the low v cc that may be present during the supply ramp. table 11-1. system status and control register (cpu_scr) [0xff] [r/w] bit # 7 6 5 4 3 2 1 0 field gies reserved wdrs pors sleep reserved stop read/write r ? r/c [4] r/c [4] r/w ? ? r/w default 0 0 0 1 0 0 0 0 the bits of the cpu_scr register are used to convey status a nd control of events for various functions of an encore ii device. bit 7: gies the global interrupt enable status bit is a read only status bit and its use is discouraged. the gies bit is a legacy bit, whic h was used to provide the ability to read the gie bit of the cpu_ f register. however, the cpu_f register is now readable. when this bit is set, it indicates that the gie bit in the cpu_f register is also set which, in turn, i ndicates that the microproces sor services interrupts. 0 = global interrupts disabled 1 = global interrupt enabled bit 6: reserved bit 5: wdrs the wdrs bit is set by the cpu to indicate that a wdr event ha s occurred. the user can read th is bit to determine the type of reset that has occurred. the user can clear but not set this bit. 0 = no wdr 1 = a wdr event has occurred bit 4: pors the pors bit is set by the cpu to indica te that a por event has occurred. the user can read this bit to determine the type of reset that has occurred. the user can clear but not set this bit 0 = no por 1 = a por event has occurred. ( note wdr events do not occur until this bit is cleared) bit 3: sleep set by the user to enable cpu sleep state. cpu remains in sle ep mode until any interrupt is pending. the sleep bit is covered in more detail in the section sleep mode on page 29 . 0 = normal operation 1 = sleep bit [2:1]: reserved bit 0: stop this bit is set by the user to halt the cpu. the cpu remains hal ted until a reset (wdr, por, or external reset) has taken place . if an application wants to stop code execution until a reset, the preferred method is to use the halt instruction rather than w riting to this bit. 0 = normal cpu operation 1 = cpu is halted (not recommended) note 4. c = clear. this bit is cleared only by the user and cannot be set by firmware. [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 29 of 86 11.1 power on reset por occurs every time the power to the device is switched on. por is released when the supply is typically 2.6v for the upward supply transition, with typically 50 mv of hysteresis during the power on transient. bit 4 of th e system status and control register (cpu_scr) is set to re cord this event (the register contents are set to 00010000 by the por). after a por, the microprocessor is held off for approximately 20 ms for the v cc supply to stabilize before exec uting the first instruction at address 0x00 in the flash. if the v cc voltage drops below the por downward supply trip point, por is reasserted. the v cc supply must ramp linearly from 0 to 4v in less than 200 ms. note the pors status bit is set at por and is cleared only by the user. it cannot be set by firmware. 11.2 watchdog timer reset the user has the option to enable the wdt. the wdt is enabled by clearing the pors bit. after the pors bit is cleared, the wdt cannot be disabled. the only exce ption to this is if a por event takes place, which disables the wdt. the sleep timer is used to generate the sleep time period and the watchdog time period. the sleep timer uses the internal 32 khz low power oscillator system clock to produce the sleep time period. the user can program the sleep time period using the sleep timer bits of the osc_cr0 register ( table 10-4 on page 24 ). when the sleep time elapses (sleep timer overflows), an interrupt to the sleep timer interrupt vector is generated. the watchdog timer period is automatically set to be three counts of the sleep timer overflow. this represents between two and three sleep intervals depending on the count in the sleep timer at the previous wdt clear. when this timer reaches three, a wdr is generated. the user can either clear the wdt, or the wdt and the sleep timer. when the user writes to the reset wdt register (res_wdt), the wdt is cleared. if the data that is written is the hex value 0x38, the sleep timer is also cleared at the same time. 12. sleep mode the cpu is put to sleep only by the firmware. this is accomplished by setting the sleep bit in the system status and control register (cpu_scr). this stops the cpu from executing instructions, and the cpu remains asleep until an interrupt comes pending, or there is a reset event (either a power on reset, or a watchdog timer reset). the low voltage detection circuit (lvd) drops into fully functional power reduced states, and the latency for the lvd is increased. the actual latency is traded against power consumption by changing sleep duty cycle field of the eco_tr register. the internal 32 khz low speed oscillator remains running. before entering the suspend mode, the firmware can optionally configure the 32 khz low speed oscillator to operate in a low power mode to help reduce the over all power consumption (using bit 7, table 10-2 on page 23 ). this helps save approximately 5 ? a; however, the trade off is that the 32 khz low speed oscillator is less accurate. all interrupts remain active. only the occurrence of an interrupt wakes the part from sleep. the st op bit in the system status and control register (cpu_scr) must be cleared for a part to resume out of sleep. the global interrupt enable bit of the cpu flags register (cpu_f) does not have any effect. any unmasked interrupt wakes the system up. as a result, any interrupts not intended for waking must be disabled through the interrupt mask registers. when the cpu enters sleep mode the cpuclk select (bit 1, table 10-3 on page 23 ) is forced to the internal oscillator. the internal oscillator recovery time is three clock cycles of the internal 32 khz low power osc illator. the internal 24 mhz oscillator restarts immediately on exiting sleep mode. if an external clock is used, firmware switches the clock source for the cpu. on exiting sleep mode, after the clock is stable and the delay time has expired, the instruction immediately following the sleep instruction is executed before the interrupt service routine (if enabled). the sleep interrupt allows the microcontroller to wake up periodically and poll system com ponents while maintaining very low average power consumption. the sleep interrupt may also be used to provide periodic interrupts during non-sleep modes. table 11-2. reset watchdog timer (reswdt) [0xe3] [w] bit # 7 6 5 4 3 2 1 0 field reset watchdog timer [7:0] read/write w w w w w w w w default 0 0 0 0 0 0 0 0 any write to this register clears watchdog timer; a write of 0x38 also clears the sleep timer. bit [7:0]: reset watchdog timer [7:0] [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 30 of 86 12.1 sleep sequence the sleep bit is an input into the sleep logic circuit. this circuit is designed to sequence the device into and out of the hardware sleep state. the hardware sequence to put the device to sleep is shown in figure 12-1 and is defined as follows. 1. firmware sets the sleep bit in the cpu_scr0 register. the bus request (brq) signal to the cpu is immediately asserted. this is a request by the system to halt cpu operation at an instruction boundary. the cpu samples brq on the positive edge of cpuclk. 2. due to the specific timing of t he register write, the cpu issues a bus request acknowledge (bra) on the following positive edge of the cpu clock. the sleep logic waits for the following negative edge of the cpu clock and then asserts a system wide power down (pd) signal. in figure 12-1 on page 30 the cpu is halted and the system wide power down signal is asserted. 3. the system wide pd (power do wn) signal controls several major circuit blocks: the flash memory module, the internal 24 mhz oscillator, the eftb filter and the bandgap voltage reference. these circuits transition into a zero power state. the only operational circuits on chip are the low power oscillator, the bandgap refresh circuit, and the supply voltage. monitor. (por/lvd) circuit. figure 12-1. sleep timing 12.2 wake up sequence once asleep, the only event that can wake the system up is an interrupt. the global interrupt enable of the cpu flag register is not required to be set. any unm asked interrupt wakes the system up. it is optional for the cpu to actually take the interrupt after the wake up sequence. the wake up sequence is synchronized to the 32 khz clock for purposes of sequencing a startup delay, to allow the flash memory module enough time to power up before the cpu asserts the first read access. another reason for the delay is to allow the o scillator, bandgap, and lvd/por circuits time to settle before actually being used in the system. as shown in figure 12-2 on page 31 , the wake up sequence is as follows: 1. the wake up interrupt occurs and is synchronized by the neg - ative edge of the 32 khz clock. 2. at the following positive edge of the 32 khz clock, the system wide pd signal is negated. the flash memory module, internal oscillator, eftb, and bandgap circuit are all powered up to a normal operating state. 3. at the following positive edge of the 32 khz clock, the current values for the precision por and lvd have settled and are sampled. 4. at the following negative edge of the 32 khz clock (after about 15 s nominal), the brq signal is negated by the sleep logic circuit. on the following cpuclk, bra is negated by the cpu and instruction execution resumes. note that in figure 12-2 on page 31 fixed function blocks, such as flash, internal oscillator, eftb, and bandgap, have about 15 sec start up. the wakeup times (interrupt to cpu operational) range from 75 s to 105 s. firmware write to scr sleep bit causes an immediate brq iow sleep brq pd bra cpuclk cpu captures brq on next cpuclk edge cpu responds with a bra on the falling edge of cpuclk, pd is asserted. the 24/48 mhz system clock is halted; the flash and bandgap are powered down [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 31 of 86 12.3 low power in sleep mode to achieve the lowest possible power consumption during suspend or sleep, the following conditions must be observed in addition to considerations for the sleep timer: 1. all gpios must be set to outputs and driven low. 2. clear p11cr[0], p10cr[0] - during usb and non-usb opera - tions 3. clear the usb enable usbcr[7] - during usb mode opera - tions 4. set p10cr[1] - during non-usb mode operations 5. make sure 32 khz oscillator clock is not selected as clock source to itmrclk, tcapclk. not even as clock output source, onto either p01_clkout or p12_vreg pins. all the other blocks go to the power down mo de automatically on suspend. the following steps are user configurable and help in reducing the average suspend mode power consumption. 1. configure the power supply monitor at a large regular inter - vals, control register bits are 1,eb[7:6] (power system sleep duty cycle pssdc[1:0]). 2. configure the low power oscillator into low power mode, control register bit is lopsctr[7]. for low power considerations during sleep when external clock is used as the cpuclk source, the clock source must be held low to avoid unintentional leakage current. if the clock is held high, then there may be a leakage through m8c. to avoid current consumption make sure itmrclk, tcpclk, and usbclk are not sourced by either low power 32 khz oscillator or 24 mhz crystal-less oscillator. do not sele ct 24 mhz or 32 khz oscillator clocks on to the p01_ clkout/p12_vreg pin. note in case of a self powered designs, particularly battery power, the usb suspend current specifications may not be met because the usb pins are expecting termination. figure 12-2. wake up timing int sleep pd lvd ppor bandgap clk32k sample sample lvd/ por cpuclk/ 24mhz bra brq enable cpu (not to scale) sleep timer or gpio interrupt occurs interrupt is double sampled by 32k clock and pd is negated to system cpu is restarted after 90ms (nominal) [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 32 of 86 13. low voltage detect control table 13-1. low voltage control register (lvdcr) [0x1e3] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved porlev[1:0] reserved vm[2:0] read/write ? ? r/w r/w ?r/w r/w r/w default 0 0 0 0 00 0 0 this register controls the configuration of the power on reset/low voltage detection block. note this register exists in the second bank of io space. this requires setting the xio bi t in the cpu flags register. bit [7:6]: reserved bit [5:4]: porlev[1:0] this field controls the level below which the precis ion power on reset (ppor) detector generates a reset. 0 0 = 2.7v range (trip near 2.6v) 0 1 = 3v range (trip near 2.9v) 1 0 = 5v range, > 4.75v (trip near 4.65v). this setting must be used when operating the cpu above 12 mhz. 1 1 = ppor does not generate a reset, but values re ad from the voltage monitor comparators register ( table 13-2 ) give the internal ppor comparator state with trip point set to the 3v range setting. bit 3: reserved bit [2:0]: vm[2:0] vm[2:0] lvd trip point (v) min lvd trip point (v) typ lvd trip point (v) max 000 reserved reserved reserved 001 reserved reserved reserved 010 reserved reserved reserved 011 reserved reserved reserved 100 4.439 4.48 4.528 101 4.597 4.64 4.689 110 4.680 4.73 4.774 111 4.766 4.82 4.862 [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 33 of 86 13.0.1 eco trim register table 13-2. voltage monitor comparators register (vltcmp) [0x1e4] [r] bit # 7 6 5 4 3 2 1 0 field reserved lvd ppor read/write ? ? ? ? ? ? r r default 0 0 0 0 0 0 0 0 this read only register allows reading the current state of the low-voltage-detection and precision-power-on-reset compar - ators bit [7:2]: reserved bit 1: lvd this bit is set to indicate that the low-voltage-detect comparat or has tripped, indicating that the supply voltage has gone bel ow the trip point set by vm[2:0] (see table 13-1 ) 0 = no low-voltage-detect event 1 = a low-voltage-detect has tripped bit 0: ppor this bit is set to indicate that the prec ision-power-on-reset comparator has tripped, indicating that the supply voltage is bel ow the trip point set by porlev[1:0] 0 = no precision-power-on-reset event 1 = a precision-power-on-reset event has occurred note this register exists in the second bank of i/o space. th is requires setting the xio bi t in the cpu flags register. table 13-3. eco (eco_tr) [0x1eb] [r/w] bit # 7 6 5 4 3 2 1 0 field sleep duty cycle [1:0] reserved read/write r/w r/w ? ? ? ? ? ? default 0 0 0 0 00 0 0 this register controls the ratios (in num bers of 32 khz clock periods) of ?on? time versus ?off? time for lvd and por detection circuit. bit [7:6]: sleep duty cycle [1:0] 0 0 = 1/128 periods of the internal 32 khz low-speed oscillator 0 1 = 1/512 periods of the internal 32 khz low-speed oscillator 1 0 = 1/32 periods of the inter nal 32 khz low-speed oscillator 1 1 = 1/8 periods of the internal 32 khz low-speed oscillator note this register exists in the second bank of i/o space. th is requires setting the xio bi t in the cpu flags register. [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 34 of 86 14. general purpose i/o (gpio) ports 14.1 port data registers table 14-1. p0 data register (p0data)[0x00] [r/w] bit # 7 6 5 4 3 2 1 0 field p0.7 p0.6/tio1 p0.5/tio0 p0.4/int2 p0.3/int1 p0.2/int0 p0.1/clkout p0.0/clkin read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 this register contains the data for port 0. writing to this regi ster sets the bit values to be output on output enabled pins. r eading from this register returns the current state of the port 0 pins. bit 7: p0.7 data p0.7 only exists in the cy7c638xx bit [6:5]: p0.6?p0.5 data/tio1 and tio0 besides their use as the p0.6?p0. 5 gpios, these pins are also used for the alte rnate functions as the capture timer input or timer output pins (tio1 and tio0). to configure the p0.5 and p0 .6 pins, refer to the p0.5/tio0? p0.6/tio1 configuration register ( table 14-4 on page 38 ). the use of the pins as the p0.6?p0.5 gpios and the al ternate functions exist in all the encore ii parts. bit [4:2]: p0.4?p0.2 data/int2 ? int0 besides their use as the p0.4?p0. 2 gpios, these pins are also used for the alte rnate functions as the in terrupt pins (int0?int2 ). to configure the p0.4?p0.2 pins, refer to the p0.2/int0?p0.4/int2 configuration register ( table 14-3 on page 38 ). the use of the pins as the p0.4?p0.2 gpios and the al ternate functions exist in all the encore ii parts. bit 1: p0.1/clkout besides its use as the p0.1 gpio, this pin is also used for an al ternate function as the clk out pin. to configure the p0.1 pin , refer to the p0.1/clkout configuration register ( table 14-2 on page 37 ). bit 0: p0.0/clkin besides its use as the p0.0 gpio, this pin is also used for an alternate function as the clkin pin. to configure the p0.0 pin, refer to the p0.0/clkin configuration register ( table 14-1 on page 37 ). [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 35 of 86 table 14-2. p1 data regist er (p1data) [0x01] [r/w] bit # 7 6 5 4 3 2 1 0 field p1.7 p1.6/smiso p1.5/smosi p1.4/sclk p1.3/ssel p1.2/vreg p1.1/d? p1.0/d+ read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 this register contains the data for port 1. writing to this regi ster sets the bit values to be output on output enabled pins. r eading from this register returns the current state of the port 1 pins. bit 7: p1.7 data p1.7 only exists in the cy7c638xx. bit [6:3]: p1.6?p1.3 data/spi pins (smiso, smosi, sclk, ssel) besides their use as the p1.6?p1. 3 gpios, these pins are also used for the alte rnate function as the spi interface pins. to configure the p1.6?p1.3 pins, refer to the p1.3?p1.6 config uration register ( table 14-9 on page 40 ). the use of the pins as the p1.6?p1.3 gpios and the al ternate functions exist in all the encore ii parts. bit 2: p1.2/vreg on the cy7c638x3, this pin is used as the p1.2 gpio or the vreg output. if the vr eg output is enabled (bit 0 ? table 19-1 on page 58 is set), a 3.3v source is placed on the pi n and the gpio function of the pin is disabled. the vreg functionality is not present in the cy7c63310 and the cy7c63801 variants. a 1 ? f min, 2 ? f max capacitor is required on vreg output. bit [1:0]: p1.1?p1.0/d? and d+ when the usb mode is disabled (bit 7 in table 21-1 on page 59 is clear), the p1.1 and p1.0 bits are used to control the state of the p1.0 and p1.1 pins. when the usb mode is enabled, the p1.1 and p1.0 pins are used as the d? and d+ pins respectively. if the usb force state bit (bit 0 in table 19-1 ) is set, the state of the d? and d+ pins ar e controlled by writing to the d? and d+ bits. table 14-3. p2 data regist er (p2data) [0x02] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved p2.1?p2.0 read/write - - - - - - r/w r/w default 0 0 0 0 0 0 0 0 this register contains the data for port 2. writing to this regi ster sets the bit values to ou tput on output enabled pins. read ing from this register returns the current state of the port 2 pins. bit [7:2]: reserved data [7:2] bit [1:0]: p2 data [1:0] p2.1?p2.0 only exist in the cy7c638(2/3)3. table 14-4. p3 data regist er (p3data) [0x03] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved p3.1?p3.0 read/write ? ? ? ? ? ? r/w r/w default 0 0 0 0 0 0 0 0 this register contains the data for port 3. writing to this regi ster sets the bit values to be output on output enabled pins. r eading from this register returns the current state of the port 3 pins. bit [7:2]: reserved data [7:2] bit [1:0]: p3 data [1:0] p3.1?p3.0 only exist in the cy7c638(2/3)3. [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 36 of 86 14.2 gpio port configuration all the gpio configuration regi sters have common configuration controls. the following are the bit definitions of the gpio configuration registers. 14.2.1 int enable when set, the int enable bit allows the gpio to generate interrupts. interrupt generate can occur regardless of whether the pin is configured for input or output. all interrupts are edge sensitive; however for any interrupt that is shared by multiple sources (that is, ports 2, 3, and 4) all inputs must be deasserted before a new interrupt can occur. when clear, the corresponding interrupt is disabled on the pin. it is possible to configure gpios as outputs, enable the interrupt on the pin and then generate the interrupt by driving the appro - priate pin state. this is useful in tests and may have value in applications. 14.2.2 int act low when set, the corresponding interrupt is active on the falling edge. when clear, the corresponding interrupt is active on the rising edge. 14.2.3 ttl thresh when set, the input has ttl threshold. when clear, the input has standard cmos threshold. 14.2.4 high sink when set, the output can sink up to 50 ma. when clear, the output can sink up to 8 ma. only the p1.7?p1.3 have 50 ma si nk drive capability. other pins have 8 ma sink drive capability. 14.2.5 open drain when set, the output on the pin is determined by the port data register. if the corresponding bit in the port data register is set, the pin is in high impedance state. if the corresponding bit in the port data register is clear, the pin is driven low. when clear, the output is driven low or high. 14.2.6 pull-up enable when set the pin has a 7 k pull-up to v cc (or vreg for ports with v3.3 enabled). when clear, the pull-up is disabled. 14.2.7 output enable when set, the output driv er of the pin is enabled. when clear, the output driver of the pin is disabled. for pins with shared functions there are some special cases. 14.2.8 vreg output/spi use the p1.2(vreg), p1.3(ssel), p1.4(sclk), p1.5(smosi) and p1.6(smiso) pins are used for their dedicated functions or for gpio. to enable the pin for gpio, clear the corresponding vreg output or spi use bit. the spi function controls the output enable for its dedicated function pins when their gpio enable bit is clear. the vreg output is not available on the cy7c63801 and cy7c63310. 14.2.9 3.3v drive the p1.3(ssel), p1.4(sclk), p1.5(smosi) and p1.6(smiso) pins have an alternate voltage source from the voltage regulator. if the 3.3v drive bit is set a high level is driven from the voltage regulator instead of from v cc . setting the 3.3 v drive bit does not enable the voltage regulator. that must be done explicitly by setting the vreg enable bit in the vregcr register ( table 19-1 on page 58 ). [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 37 of 86 figure 14-1. block diagram of a gpio v cc vreg v cc vreg gpio pin r up data out v cc gnd vreg gnd 3.3v drive pull-up enable output enable open drain port data high sink data in ttl threshold table 14-1. p0.0/clkin configuration (p00cr) [0x05] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved int enable int act low ttl thresh reserved open drain pull-up enable output enable read/write ? r/w r/w r/w ? r/w r/w r/w default 0 0 0 0 0 0 0 0 this pin is shared between the p0.0 gpio use and the clkin pin fo r an external clock. when the external clock input is enabled (bit[0] in register cpuclkcr ta b l e 10-3 on page 23 ) the settings of this register are ignored. the use of the pin as the p0.0 gpio is available in all the encore ii parts. table 14-2. p0.1/clkout configuration (p01cr) [0x06] r/w] bit # 7 6 5 4 3 2 1 0 field clk output int enable int act low ttl thresh reserved open drain pull-up enable output enable read/write r/w r/w r/w r/w ? r/w r/w r/w default 0 0 0 0 0 0 0 0 this pin is shared between the p0.1 gpio use and the clkout pi n. when clk output is set, th e internally selected clock is sent out onto p0.1clkout pin. the use of the pin as the p0.1 gpio is available in all the encore ii parts. bit 7: clk output 0 = the clock output is disabled. 1 = the clock selected by the clk select fi eld (bit [1:0] of the clkiocr register ( table 10-1 on page 27 ) is driven out to the pin. [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 38 of 86 table 14-3. p0.2/int0?p0.4/int2 configuration (p02cr?p04cr) [0x07?0x09] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved int act low ttl thresh reserved open drain pull-up enable output enable read/write ? ? r/w r/w ? r/w r/w r/w default 0 0 0 0 0 0 0 0 these registers control the operation of pi ns p0.2?p0.4 respectively. the pins are shared between the p0.2?p0.4 gpios and the int0?int2. these registers exist in all encore ii parts. the int0?int2 interrupts are diff erent from all the other gpio interrupts. these pins are connected direct ly to the interrupt controller to provi de three edge sensitive interrupts with indep endent interrupt vectors. these interrupts occur on a rising edge when int act low is clear and on a falling edge when int act low is set. the pins are enabled as interrupt sources in the interrupt controller registers ( table 17-7 on page 56 and table 17-5 on page 54 ). to use these pins as interrupt inputs, configure them as inputs by clearing the corresponding output enable. if the int0?int2 pins are configured as outputs with inte rrupts enabled, firmware can generate an inte rrupt by writing the appropriate value to the p0.2, p0.3 and p0.4 data bits in the p0 data register. regardless of whether the pins are used as interrupt or gpio pi ns the int enable, int act low, ttl threshold, open drain, and pull-up enable bits control the behavior of the pin. the p0.2/int0?p0.4/int2 pins are individually configured wit h the p02cr (0x07), p03cr (0x08), and p04cr (0x09) respec - tively. note changing the state of the int act low bit can cause an unint entional interrupt to be generated. when configuring these interrupt sources, it is best to follow the following procedure: 1. disable interrupt source 2. configure interrupt source 3. clear any pending interrupts from the source 4. enable interrupt source table 14-4. p0.5/tio0 ? p0.6/tio1 configuration (p05cr?p06cr) [0x0a?0x0b] [r/w] bit # 7 6 5 4 3 2 1 0 field tio output int enable int act low ttl thresh reserved open drain pull-up enable output enable read/write ? r/w r/w r/w ? r/w r/w r/w default 0 0 0 0 0 0 0 0 these registers control the operation of pins p0.5 through p0.6 , respectively. these registers exist in all encore ii parts. p0.5 and p0.6 are shared with tio0 and tio1, respectively. to use these pins as capture timer inputs, configure them as inputs by clearing the corresponding output enable. to use tio0 and ti o1 as timer outputs, set the tiox output and output enable bits. if these pins are configured as outputs and the tio output bit is clear, firmware can control the tio0 and tio1 inputs by writing the value to the p0.5 and p0.6 data bits in the p0 data register. regardless of whether either pin is used as a tio or gpio pi n the int enable, int act low, ttl threshold, open drain, and pull-up enable control the behavior of the pin. tio0(p0.5) when enabled outputs a positive pulse from the free r unning timer. this is the same signal that is used internally to generate the 1024 ? s timer interrupt. this signal is not gated by the inte rrupt enable state. the pulse is active for one cycle of the capture timer clock. tio1(p0.6) when enabled outputs a positive pulse from the progra mmable interval timer. this is the same signal that is used internally to generate the programmable timer interval interrupt. this signal is not gated by th e interrupt enable state. the p ulse is active for one cycle of the interval timer clock. the p0.5/tio0 and p0.6/tio1 pins are individually configur ed with the p05cr (0x0a) and p06cr (0x0b), respectively. [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 39 of 86 table 14-5. p0.7 configuration (p07cr) [0x0c] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved int enable int act low ttl thresh reserved open drain pull-up enable output enable read/write ? r/w r/w r/w ? r/w r/w r/w default 0 0 0 0 0 0 0 0 this register controls the operation of pin p0.7 . the p0.7 pin only exists in the cy7c638(1/2/3)3. table 14-6. p1.0/d+ configuration (p10cr) [0x0d] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved int enable int act low reserved ps/2 pull-up enable output enable read/write r/w r/w r/w ? ? ? r/w r/w default 0 0 0 0 0 0 0 0 this register controls the operation of the p1.0 (d+) pin wh en the usb interface is not enabled, allowing the pin to be used as a ps2 interface or a gpio. see table 21-1 on page 59 for information on enabling the usb. when the usb is enabled, none of the controls in this register have any affect on the p1.0 pin. note the p1.0 is an open drain only output. it can actively drive a signal low, but cannot actively drive a signal high. bit 1: ps/2 pull-up enable 0 = disable the 5k ohm pull-up resistors 1 = enable 5k ohm pull-up resistors for both p1.0 and p1.1. enable the use of the p1.0 (d+) and p1.1 (d?) pins as a ps2 style interface. table 14-7. p1.1/d? configur ation (p11cr) [0x0e] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved int enable int act low reserved open drain reserved output enable read/write ? r/w r/w ? ? r/w ? r/w default 0 0 0 0 0 0 0 0 this register controls the operation of the p1.1 (d?) pin when the usb interface is not enabled, allowing the pin to be used as a ps2 interface or a gpio. see table 21-1 on page 59 for information on enabling usb. when usb is enabled, none of the controls in this register have any affect on the p1.1 pin. when usb is disabled, the 5k ohm pull-up resistor on this pin may be enabled by the ps/2 pull-up enable bit of the p10cr register ( table 14-6 ) note there is no 2 ma sourcing capability on this pin. the pin can only sink 5 ma at v ol3 (see section dc characteristics on page 69 ) table 14-8. p1.2 configuration (p12cr) [0x0f] [r/w] bit # 7 6 5 4 3 2 1 0 field clk output int enable int act low ttl threshold reserved open drain pull-up enable output enable read/write r/w r/w r/w r/w ? r/w r/w r/w default 0 0 0 0 0 0 0 0 this register controls the operation of the p1.2. bit 7: clk output 0 = the internally selected clock is not sent out onto p1.2 pin 1 = when clk output is set, the internally selected clock is sent out onto p1.2 pin note: ta b l e 10-1, ?clock io config (clkiocr) [0x32] [r/w],? on page 27 is used to select the external or internal clock in encore ii devices [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 40 of 86 table 14-9. p1.3 configuration (p13cr) [0x10] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved int enable int act low 3.3v drive high sink open drain pull-up enable output enable read/write ? r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 this register controls the operation of the p1.3 pin. this register exists in all encore ii parts. the p1.3 gpio?s threshold is always set to ttl. when the spi hardware is enabled or disabled, the pin is contro lled by the output enable bit and the corresponding bit in the p1 data register. regardless of whether the pin is used as an spi or gpio pin the int enable, int act lo w, 3.3v drive, high sink, open drain, and pull-up enable control the behavior of the pin. table 14-10. p1.4?p1.6 configuration (p14cr?p16cr) [0x11?0x13] [r/w] bit # 7 6 5 4 3 2 1 0 field spi use int enable int act low 3.3v drive high sink open drain pull-up enable output enable read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 these registers control the operation of pins p1.4?p1.6, respectively. these re gisters exist in all encore ii parts. bit 7: spi use 0 = disable the spi alternate function. the pin is used as a gpio 1 = enable the spi function. the spi circ uitry controls the output of the pin the p1.4?p1.6 gpio?s threshold is always set to ttl. when the spi hardware is enabled, pins that are configured as spi use have their output enabl e and output state controlled by the spi circuitry. when the spi hardware is disabled or a pin has its spi use bit clear, the pin is controlled by the output en able bit and the corresponding bit in the p1 data register. regardless of whether any pin is used as an spi or gpio pin the int enable, int act low, 3.3v drive, high sink, open drain, and pull-up enable control the behavior of the pin. note for comm modes 01 or 10 ( spi master or spi slave, see table 15-2 on page 42 ) when configured for spi (spi use = 1 and comm modes [1:0] = spi master or spi slav e mode), the input and output direction of pins p1.5, and p1.6 is set automatically by the spi logic. however, pin p1 .4's input and output direction is not automatical ly set; it must be explicitly set by firmwar e. for spi master mode, pin p1.4 must be co nfigured as an output; for spi slave mode, pin p1.4 must be configured as an input. table 14-11. p1.7 configuration (p17cr) [0x14] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved int enable int act low reserved high sink open drain pull-up enable output enable read/write ? r/w r/w ? r/w r/w r/w r/w default 0 0 0 0 0 0 1 0 this register controls the operation of pin p1.7. this register only exists in cy7c638(1/2/3)3. the p1.7 gpio?s threshold is always set to ttl. table 14-12. p2 configuration (p2cr) [0x15] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved int enable int act low ttl thresh reserved open drain pull-up enable output enable read/write ? r/w r/w r/w ? r/w r/w r/w default 0 0 0 0 0 0 0 0 this register only exists in cy7c638(2/3)3. this register controls the ope ration of pins p2.0?p2.1. [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 41 of 86 15. serial peripheral interface (spi) the spi master/slave interface core logic runs on the spi clock domain, so that its functionality is independent of system cloc k speed. spi is a four pin serial interface comprise d of a clock, an enable and two data pins. 15.1 spi data register when an interrupt occurs to indicate to the firmware that a byte of receive data is available, or the transmitter holding regis ter is empty, the firmware has 7 spi clocks to manage the buffers: to empty the re ceiver buffer or to refill the transmit holding register. f ailure to meet this timing requirement results in incorrect data transfer. table 14-13. p3 configuration (p3cr) [0x16] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved int enable int act low ttl thresh reserved open drain pull-up enable output enable read/write ? r/w r/w r/w ? r/w r/w r/w default 0 0 0 0 0 0 1 0 this register exists in cy7c638(2/3)3. this re gister controls the oper ation of pins p3.0?p3.1. table 15-1. spi data register (spidata) [0x3c] [r/w] bit # 7 6 5 4 3 2 1 0 field spidata[7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 when read, this register returns the cont ents of the receive buffer. when written, it loads the transmit holding register. bit [7:0]: spi data [7:0] [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 42 of 86 15.2 spi configure register table 15-2. spi configure register (spicr) [0x3d] [r/w] bit # 7 6 5 4 3 2 1 0 field swap lsb first comm mode cpol cpha sclk select read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit 7: swap 0 = swap function disabled. 1 = the spi block swaps its use of smosi and smiso. this is us eful in implementing single wire communications similar to spi. bit 6: lsb first 0 = the spi transmits and receives the msb (most significant bit) first. 1 = the spi transmits and receives the lsb (least significant bit) first. bit [5:4]: comm mode [1:0] 0 0: all spi communication disabled. 0 1: spi master mode 1 0: spi slave mode 1 1: reserved bit 3: cpol this bit controls the spi clock (sclk) idle polarity. 0 = sclk idles low 1 = sclk idles high bit 2: cpha the clock phase bit controls the phase of the clock on which data is sampled. table 15-4 on page 43 shows the timing for the various combinations of lsb first, cpol, and cpha. bit [1:0]: sclk select this field selects the speed of the master sclk. when in master mode, sclk is generate d by dividing the base cpuclk. note for comm modes 01b or 10b (spi master or spi slave) when configured for spi, (spi use = 1 table 14-10 on page 40 ), the input/output direction of pins p1.3, p1.5, and p1.6 is set automatically by the spi logic. however, pin p1.4's input/output direction is no t automatically set; it must be explicitly set by firmware. for spi master mode, pin p1.4 must be configured as an output; for spi slave mode, pin p1.4 must be configured as an input. table 15-3. spi sclk frequency sclk ? select cpuclk ? divisor sclk frequency when cpuclk = 12 mhz 24 mhz 00 6 2 mhz 4 mhz 01 12 1 mhz 2 mhz 10 48 250 khz 500 khz 11 96 125 khz 250 khz [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 43 of 86 15.3 spi interface pins the spi interface uses the p1.3?p1.6 pins. these pins ar e configured using the p1.3 and p1.4?p1.6 configuration. table 15-4. spi mode timing vs. lsb first, cpol and cpha lsb first cpha cpol diagram 000 001 010 011 100 101 110 111 sclk ssel data x x msb bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb sclk ssel x x data msb bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb sclk ssel x x data msb bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb sclk ssel data x x msb bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb sclk ssel data x x msb bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb sclk ssel x x data msb bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb sclk ssel x x data msb bit 2bit 3bit 4bit 5bit 6bit 7 lsb sclk ssel data x msb x bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 44 of 86 16. timer registers all timer functions of the encore ii are provided by a single ti mer block. the timer block is asynchronous from the cpu clock. 16.1 registers 16.1.1 free running counter the 16 bit free-running counter is clocked by the timer capture clock (tcapclk). it is read in software for use as a general pu rpose time base. when the low order byte is read, the high order byte is registered. reading the high order byte reads this register, allowing the cpu to read the 16-bit value atomically (loads all bits at one time). the free-running timer generates an interrupt at 1024 ? s rate when clocked by a 4 mhz source. it also generates an interru pt when the free running counter overflow occurs every 16.384 ms (with a 4 mhz source). this allows extending the length of the timer in software. figure 16-1. 16-bit free ru nning counter block diagram timer capture clock 16-bit free running counter overflow interrupt/w rap interrupt 1024 s timer interrupt table 16-1. free running timer low order byte (frtmrl) [0x20] [r/w] bit # 7 6 5 4 3 2 1 0 field free running timer [7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit [7:0]: free running timer [7:0] this register holds the low order byte of the 16-bit free running timer. reading this register causes the high order byte to be moved into a holding register allowing an automatic read of all 16 bits simultaneously. for reads, the actual read occurs in the cycle when the low orde r is read. for writes, the actual time the write occurs is the cycle when the high order is written. when reading the free running timer, the low order byte must be read first and the high order second. when writing, the low order byte must be written fi rst then the high order byte. table 16-2. free running timer high-order byte (frtmrh) [0x21] [r/w] bit # 7 6 5 4 3 2 1 0 field free-running timer [15:8] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit [7:0]: free-running timer [15:8] when reading the free-running timer, the low order byte must be read first and the high order second. when writing, the low order byte must be written fi rst then the high order byte. [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 45 of 86 table 16-3. timer capture 0 rising (tio0r) [0x22] [r/w] bit # 7 6 5 4 3 2 1 0 field capture 0 rising [7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit [7:0]: capture 0 rising [7:0] this register holds the value of the free-running timer when the last rising edge occurred on the tio0 input. when capture 0 is in 8-bit mode, the bits that are stored here are selected by the prescale [2:0] bits in the timer configuration register. wh en capture 0 is in 16-bit mode this register ho lds the lower order 8 bits of the 16-bit timer. table 16-4. timer capture 1 rising (tio1r) [0x23] [r/w] bit # 7 6 5 4 3 2 1 0 field capture 1 rising [7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit [7:0]: capture 1 rising [7:0] this register holds the value of the free-running timer when the last rising ed ge occurred on the tio1 input in the 8-bit mode. the bits that are stored here are selected by the prescale [2:0 ] bits in the timer configuration register. when capture 0 is in 16-bit mode this register holds the high order 8 bits of the 16-bit timer from the last capture 0 rising edge. table 16-5. timer capture 0 falling (tio0f) [0x24] [r/w] bit # 7 6 5 4 3 2 1 0 field capture 0 falling [7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit [7:0]: capture 0 falling [7:0] this register holds the value of the free-running timer when the last falling edge occurred on the tio0 input. when capture 0 is in 8-bit mode, the bits that are stored here are selected by the prescale [2:0] bits in the timer configuration register. wh en capture 0 is in 16-bit mode this register ho lds the lower order 8 bits of the 16-bit timer. table 16-6. timer capture 1 falling (tio1f) [0x25] [r/w] bit # 7 6 5 4 3 2 1 0 field capture 1 falling [7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit [7:0]: capture 1falling [7:0] this register holds the value of the free-running timer when th e last falling edge occurred on the tio1 input in the 8-bit mode . the bits that are stored here are selected by the prescale [2:0 ] bits in the timer configuration register. when capture 0 is in 16-bit mode this register holds the high order 8 bits of the 16-bit timer from the last capture 0 falling edge. table 16-7. programmable interval timer low (pitmrl) [0x26] [r] bit # 7 6 5 4 3 2 1 0 field prog interval timer [7:0] read/write r r r r r r r r default 0 0 0 0 0 0 0 0 bit [7:0]: prog interval timer [7:0] this register holds the low order byte of the 12-bit programmable interval timer. read ing this register causes the high order b yte to be moved into a holding register allowing an automatic read of all 12 bits simultaneously. [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 46 of 86 table 16-8. programmable interval timer high (pitmrh) [0x27] [r] bit # 7 6 5 4 3 2 1 0 field reserved prog interval timer [11:8] read/write ? ? ? ? r r r r default 0 0 0 0 0 0 0 0 bit [7:4]: reserved bit [3:0]: prog internal timer [11:8] this register holds the high order nibble of the 12-bit programm able interval timer. reading this register returns the high ord er nibble of the 12-bit timer at the instant that the low order byte was last read. table 16-9. programmable interval reload low (pirl) [0x28] [r/w] bit # 7 6 5 4 3 2 1 0 field prog interval [7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit [7:0]: prog interval [7:0] this register holds the lower 8 bits of the timer. when writing into the 12-bit reload register, write the lower byte first the n the higher nibble. table 16-10. programmable interval reload high (pirh) [0x29] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved prog interval[11:8] read/write ? ? ? ? r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit [7:4]: reserved bit [3:0]: prog interval [11:8] this register holds the higher 4 bits of the timer. while writi ng into the 12-bit reload register , write the lower byte first t hen the higher nibble. figure 16-2. programmable interval timer block diagram system clock c lock tim er configuration status and control 12-bit reload value 12-bit dow n counter 12-bit reload counter in te rru p t c ontroller [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 47 of 86 16.1.2 timer capture cypress encore ii has two 8-bit captures. each capture has sepa rate registers for the rising and falling time. the two eight bi t captures can be configured as a single 16-bit captur e. when configured, the capture 1 registers hold the high order byte of the 16-bit t imer capture value. each of the four capture registers may be programmed to generate an interrupt when it is loaded. table 16-1. timer configur ation (tmrcr) [0x2a] [r/w] bit # 7 6 5 4 3 2 1 0 field first edge hold 8-bit capture prescale [2:0] cap0 16bit enable reserved read/write r/w r/w r/w r/w r/w ? ? ? default 0 0 0 0 0 0 0 0 bit 7: first edge hold the first edge hold function applies to all four capture timers. 0 = the time of the most recent edge is held in the capture ti mer data register. if multiple edges have occurred since reading the capture timer, the time for the most recent one is read. 1 = the time of the first occurrence of an edge is held in the capture timer data register unt il the data is read. subsequent edges are ignored until the capture timer data register is read. bit [6:4]: 8-bit capture prescale [2:0] this field controls which 8 bits of the 16 free running timer are captured when in bit mode. 0 0 0 = capture timer[7:0] 0 0 1 = capture timer[8:1] 0 1 0 = capture timer[9:2] 0 1 1 = capture timer[10:3] 1 0 0 = capture timer[11:4] 1 0 1 = capture timer[12:5] 1 1 0 = capture timer[13:6] 1 1 1 = capture timer[14:7] bit 3: cap0 16-bit enable 0 = capture 0 16-bit mode is disabled 1 = capture 0 16-bit mode is enabled. capture 1 is disabled and the capture 1 rising and falling regi sters are used as an exten sion to the capture 0 registers ?extending them to 16 bits bit [2:0]: reserved [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 48 of 86 table 16-2. capture interrupt enable (tcapinte) [0x2b] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved cap1 fall enable cap1 rise enable cap0 fall enable cap0 rise enable read/write ? ? ? ? r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit [7:4]: reserved bit 3: cap1 fall enable 0 = disable the capture 1 falling edge interrupt 1 = enable the capture 1 falling edge interrupt bit 2: cap1 rise enable 0 = disable the capture 1 rising edge interrupt 1 = enable the capture 1 rising edge interrupt bit 1: cap0 fall enable 0 = disable the capture 0 falling edge interrupt 1 = enable the capture 0 falling edge interrupt bit 0: cap0 rise enable 0 = disable the capture 0 rising edge interrupt 1 = enable the capture 0 rising edge interrupt table 16-3. capture interrupt status (tcapints) [0x2c] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved tio1 fall active tio1 rise active tio0 fall active tio0 rise active read/write ? ? ? ? r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit [7:4]: reserved bit 3: tio1 fall active 0 = no event 1 = a falling edge has occurred on tio1 bit 2: tio1 rise active 0 = no event 1 = a rising edge has occurred on tio1 bit 1: tio0 fall active 0 = no event 1 = a falling edge has occurred on tio0 bit 0: tio0 rise active 0 = no event 1 = a rising edge has occurred on tio0 note the interrupt status bits must be cleared by firmware to enabl e subsequent interrupts. this is achieved by writing a ?1? to the corresponding interrupt status bit. [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 49 of 86 figure 16-3. timer functional sequence diagram [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 50 of 86 figure 16-4. 16-bit free running counter loading timing diagram clk_sys write valid addr write data frt reload ready clk timer 12b prog timer 12b reload interrupt capture timer clk 16b free running counter load 16b free running counter 00a0 00a1 00a2 00a3 00a4 00a5 00a6 00a7 00a8 00a9 00ab 00ac 00ad 00ae 00af 00b0 00b1 00b2 acbe acbf acc0 16-bit free running counter loading timing 12-bit programmable timer load timing figure 16-5. memory mapped registers read/write timing diagram clk_sys rd_wrn valid addr rdata wdata [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 51 of 86 17. interrupt controller the interrupt controller and its associated registers allow the user?s code to respond to an interrupt from almost every functional block in the encore ii devices. the registers associated with the interrupt controller allow disabling interrupts globally or individually. the registers also provide a mechanism by which a user may clear all pending and posted interrupts, or clear individual posted or pending interrupts. the following table lists all interrupts and the priorities that are available in the encore ii devices. 17.1 architectural description an interrupt is posted when its interrupt conditions occur. this results in the flip-flop in figure 17-1 on page 52 clocking in a ?1?. the interrupt remains posted until the interrupt is taken or until it is cleared by writing to the appropriate int_clrx register. a posted interrupt is not pending unless it is enabled by setting its interrupt mask bit (in the appr opriate int_mskx register). all pending interrupts are processed by the priority encoder to determine the highest priority interrupt which is taken by the m8c if the global interrupt enable bit is set in the cpu_f register. disabling an interrupt by clearing its interrupt mask bit (in the int_mskx register) does not clear a posted interrupt, nor does it prevent an interrupt from bei ng posted. it prevents a posted interrupt from becoming pending. nested interrupts are accomplished by re-enabling interrupts inside an interrupt service routine. to do this, set the ie bit in the flag register. a block diagram of the encore ii interrupt controller is shown in figure 17-1 on page 52 . table 17-1. interrupt numbers, priorities, vectors interrupt priority interrupt address name 0 0000h reset 1 0004h por/lvd 2 0008h int0 3 000ch spi transmitter empty 4 0010h spi receiver full 5 0014h gpio port 0 6 0018h gpio port 1 7 001ch int1 8 0020h ep0 9 0024h ep1 10 0028h ep2 11 002ch usb reset 12 0030h usb active 13 0034h 1 ms interval timer 14 0038h programmable interval timer 15 003ch timer capture 0 16 0040h timer capture 1 17 0044h 16-bit free running timer wrap 18 0048h int2 19 004ch ps2 data low 20 0050h gpio port 2 21 0054h gpio port 3 22 0058h reserved 23 005ch reserved 24 0060h reserved 25 0064h sleep timer [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 52 of 86 17.2 interrupt processing the sequence of events that occur during interrupt processing follows: 1. an interrupt becomes active, because: a. the interrupt condition occurs (for example, a timer expires). b. a previously posted interrupt is enabled through an update of an interrupt mask register. c. an interrupt is pending and gie is set from 0 to 1 in the cpu flag register. 1. the current executing instruction finishes. 2. the internal interru pt is dispatched, taking 13 cycles. during this time, the following actions occur: the msb and lsb of program counter and flag registers (cpu_pc and cpu_f) are stored onto the program stack by an automatic call instruction (13 cycles) generated during the interrupt acknowledge process. a. the pch, pcl, and flag register (cpu_f) are stored onto the program stack (in that order) by an automatic call instruction (13 cycles) generated during the interrupt acknowledge process b. the cpu_f register is then cl eared. because this clears the gie bit to 0, additional interrupts are temporarily disabled. c. the pch (pc[15:8]) is cleared to zero. d. the interrupt vector is read from the interrupt controller and its value placed into pcl (pc[ 7:0]). this sets the program counter to point to the appropriate address in the interrupt table (for example, 0004h for the por/lvd interrupt). 1. program execution vectors to th e interrupt table. typically, a ljmp instruction in the interrupt table sends execution to the user's interrupt service rout ine (isr) for this interrupt. 2. the isr executes. note that interrupts are disabled because ? gie = 0. in the isr, interrupts are re-enabled by setting ? gie = 1 (care must be taken to avoid stack overflow). 3. the isr ends with a reti inst ruction which restores the program counter and flag registers (cpu_pc and cpu_f). the restored flag register re-enables interrupts, because ? gie = 1 again. 4. execution resumes at the next instruction, after the one that occurred before the interrupt. however, if there are more pending interrupts, the subsequent interrupts are processed before the next normal program instruction. 17.3 interrupt trigger conditions trigger conditions for most interrupts in table 17-1 on page 51 have been explained in the relevant sections. however, conditions under which the usb active (interrupt address 0030h) and ps2 data low (interrupt address 004ch) interrupts are triggered are explained follow. 1. usb active interrupt: triggered when the d+/- lines are in a non-idle state, that is, k-state or se0 state. 2. ps2 data low interrupt: triggered when sdata becomes low when the sdata pad is in the input mode for at least 6-7 ? 32 khz cycles. 3. the gpio interrupts are edge triggered. 17.4 interrupt latency the time between the assertion of an enabled interrupt and the start of its isr is calculated from the following equation. latency = time for current instructio n to finish + ti me for internal interrupt routine to execute + time for ljmp instruction in interrupt table to execute. for example, if the 5 cycle jmp in struction is executing when an interrupt becomes active, the to tal number of cpu clock cycles before the isr begins is as follows: (1 to 5 cycles for jmp to finish) + (13 cycles for interrupt routine) + (7 cycles for ljmp) = 21 to 25 cycles. in the previous example, at 24 mhz, 25 clock cycles take ? 1.042 ? s. figure 17-1. interrupt controller block diagram interrupt source (timer, gpio, etc.) interrupt tak en or posted interrupt pending interrupt gie interrupt vector mask bit setting d r q 1 priority encoder m8c c o r e interrupt request ... int_mskx int_clrx write cpu_f[0] ... [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 53 of 86 17.5 interrupt registers the interrupt clear registers (int_clrx) ar e used to enable the individual interrupt sources? ability to clear posted interrupt s. when an int_clrx register is read, any bits that are set indi cates an interrupt has been posted for that hardware resource. the refore, reading these registers gives the user the ability to determine all posted interrupts. 17.5.1 interrupt mask registers the interrupt mask registers (int_mskx) enable the individual interrupt sources? ability to create pending interrupts. there are four interrupt mask registers (int_msk0, int_msk1, int_msk2, and int_msk3) which may be referred to in general as int_mskx. if cleared, each bit in an int_mskx register prevents a posted interrupt from becoming a pending interrupt (input to the priority encoder). however, an interrupt can still post even if its mask bit is zero. all int_mskx bits are independent of all other int_mskx bits. if an int_mskx bit is set, the interrupt source associated with that mask bit may generate an inte rrupt that becomes a pending interrupt. the enable software interrupt (enswint) bit in int_msk3[7] determines the way an individual bit value written to an int_clrx register is interpreted. when it is cleared, writing 1's to an int_clrx register has no effect. however, writing 0's to an int_clrx register, when enswint is cleared, causes the corresponding interrupt to clear. if the enswint bit is set, any 0s written to the int_clrx registers are ignored. however, 1s written to an int_clrx register, when enswint is set, causes an interrupt to post for the corresponding interrupt. software interrupts can aid in debugging interrupt service routines by eliminating the need to create system level interac - tions that are sometimes necessa ry to create a hardware only interrupt. table 17-1. interrupt clear 0 (int_clr0) [0xda] [r/w] bit # 7 6 5 4 3 2 1 0 field gpio port 1 sleep timer int1 gpio port 0 spi receive spi transmit int0 por/lvd read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 when reading this register, 0 = there is no posted interrupt for the corresponding hardware 1 = posted interrupt for the corresponding hardware present writing a ?0? to the bits clears the posted interrupts for the co rresponding hardware. writing a ?1? to the bits and to the ens wint (bit 7 of the int_msk3 register) posts the corresponding hardware interrupt. table 17-2. interrupt clear 1 (int_clr1) [0xdb] [r/w] bit # 7 6 5 4 3 2 1 0 field tcap0 prog interval timer 1-ms timer usb active usb reset usb ep2 usb ep1 usb ep0 read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 when reading this register, 0 = there is no posted interrupt for the corresponding hardware. 1 = posted interrupt for the corresponding hardware present. writing a ?0? to the bits clears the posted interrupts for the corresponding hardware. writing a ?1? to the bits and to the ens wint (bit 7 of the int_msk3 register) posts the corresponding hardware interrupt. table 17-3. interrupt clear 2 (int_clr2) [0xdc] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved reserved gpio port 3 gpio port 2 ps/2 data low int2 16-bit counter wrap tcap1 read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 when reading this register, 0 = there is no posted interrupt for the corresponding hardware. 1 = posted interrupt for the corresponding hardware present. writing a ?0? to the bits clears the posted interrupts for the co rresponding hardware. writing a ?1? to the bits and to the ens wint (bit 7 of the int_msk3 register) posts the corresponding hardware interrupt. [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 54 of 86 table 17-4. interrupt mask 3 (int_msk3) [0xde] [r/w] bit # 7 6 5 4 3 2 1 0 field enswint reserved read/write r/w ? ? ? ? ? ? ? default 0 0 0 0 0 0 0 0 bit 7: enable software interrupt (enswint) 0= disable. writing 0s to an int_clrx register, when enswin t is cleared, causes the corresponding interrupt to clear 1= enable. writing 1s to an int_clrx register, when en swint is set, causes the corresponding interrupt to post. bit [6:0]: reserved table 17-5. interrupt mask 2 (int_msk2) [0xdf] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved reserved gpio port 3 int enable gpio port 2 int enable ps/2 data low int enable int2 int enable 16-bit counter wrap int enable tcap1 int enable read/write ? r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit 7: reserved bit 6: gpio port 4 interrupt enable 0 = mask gpio port 4 interrupt 1 = unmask gpio port 4 interrupt bit 5: gpio port 3 interrupt enable 0 = mask gpio port 3 interrupt 1 = unmask gpio port 3 interrupt bit 4: gpio port 2 interrupt enable 0 = mask gpio port 2 interrupt 1 = unmask gpio port 2 interrupt bit 3: ps/2 data low interrupt enable 0 = mask ps/2 data low interrupt 1 = unmask ps/2 data low interrupt bit 2: int2 interrupt enable 0 = mask int2 interrupt 1 = unmask int2 interrupt bit 1: 16-bit counter wrap interrupt enable 0 = mask 16-bit counter wrap interrupt 1 = unmask 16-bit counter wrap interrupt bit 0: tcap1 interrupt enable 0 = mask tcap1 interrupt 1 = unmask tcap1 interrupt [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 55 of 86 table 17-6. interrupt mask 1 (int_msk1) [0xe1] [r/w] bit # 7 6 5 4 3 2 1 0 field tcap0 int enable prog interval timer int enable 1 ms timer int enable usb active int enable usb reset int enable usb ep2 int enable usb ep1 int enable usb ep0 int enable read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit 7: tcap0 interrupt enable 0 = mask tcap0 interrupt 1 = unmask tcap0 interrupt bit 6: prog interval timer interrupt enable 0 = mask prog interval timer interrupt 1 = unmask prog interval timer interrupt bit 5: 1-ms timer interrupt enable 0 = mask 1-ms interrupt 1 = unmask 1-ms interrupt bit 4: usb active interrupt enable 0 = mask usb active interrupt 1 = unmask usb active interrupt bit 3: usb reset interrupt enable 0 = mask usb reset interrupt 1 = unmask usb reset interrupt bit 2: usb ep2 interrupt enable 0 = mask ep2 interrupt 1 = unmask ep2 interrupt bit 1: usb ep1 interrupt enable 0 = mask ep1 interrupt 1 = unmask ep1 interrupt bit 0: usb ep0 interrupt enable 0 = mask ep0 interrupt 1 = unmask ep0 interrupt [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 56 of 86 table 17-7. interrupt mask 0 (int_msk0) [0xe0] [r/w] bit # 7 6 5 4 3 2 1 0 field gpio port 1 int enable sleep timer int enable int1 int enable gpio port 0 int enable spi receive int enable spi transmit int enable int0 int enable por/lvd int enable read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit 7: gpio port 1 interrupt enable 0 = mask gpio port 1 interrupt 1 = unmask gpio port 1 interrupt bit 6: sleep timer interrupt enable 0 = mask sleep timer interrupt 1 = unmask sleep timer interrupt bit 5: int1 interrupt enable 0 = mask int1 interrupt 1 = unmask int1 interrupt bit 4: gpio port 0 interrupt enable 0 = mask gpio port 0 interrupt 1 = unmask gpio port 0 interrupt bit 3: spi receive interrupt enable 0 = mask spi receive interrupt 1 = unmask spi receive interrupt bit 2: spi transmit interrupt enable 0 = mask spi transmit interrupt 1 = unmask spi transmit interrupt bit 1: int0 interrupt enable 0 = mask int0 interrupt 1 = unmask int0 interrupt bit 0: por/lvd interrupt enable 0 = mask por/lvd interrupt 1 = unmask por/lvd interrupt table 17-8. interrupt vector clear register (int_vc) [0xe2] [r/w] bit # 7 6 5 4 3 2 1 0 field pending interrupt [7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 the interrupt vector clear register (int_vc) holds the interrupt vector for the highest priority pending interrupt when read, a nd when written clears all pending interrupts. bit [7:0]: pending interrupt [7:0] 8-bit data value holds the interrupt vector for the highest priori ty pending interrupt. writing to this register clears all pen ding interrupts. [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 57 of 86 18. regulator output 18.1 vreg control table 18-1. vreg control register (vregcr) [0x73] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved keep alive vreg enable read/write ? ? ? ? ? ? r/w r/w default 0 0 0 0 00 0 0 bit [7:2]: reserved bit 1: keep alive keep alive, when set, allows the voltage regulator to source up to 20 a of current when the voltage regulator is disabled. p12cr[0],p12cr[7] must be cleared. 0 = disabled 1 = enabled bit 0: vreg enable this bit turns on the 3.3 v voltage regulator. the voltage regulator only functions within specifications when v cc is above 4.35 v. this block must not be enabled when v cc is below 4.35v?although no damage or irregularities occur if it is enabled below 4.35 v. 0 = disable the 3.3 v voltage regulator output on the vreg/p1.2 pin. 1 = enable the 3.3 v voltage regulator output on the vr eg/p1.2 pin. gpio functiona lity of p1.2 is disabled. note use of the alternate driv e on pins p1.3?p1.6 requires that the vreg enable bit be set to enable the regulator and provide the alternate voltage. [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 58 of 86 19. usb/ps2 transceiver although the usb transceiver has features to assist in interfac ing to ps/2, these features are not controlled using these regis ters. the registers only control the usb interfacing features. ps/2 interfacing options are contro lled by the d+ and d? gpio configuratio n register (see table 14-2 on page 35 ). 19.1 usb transceiver configuration 20. usb serial in terface engine (sie) the sie allows the microcontroller to communicate with the usb host at low speed data rates (1.5 mbps). the sie simplifies the interface between the microcontroller and the usb by incorpo - rating hardware that handles the following usb bus activity independently of the microcontroller. translate the encoded received data and format the data to be transmitted on the bus. crc checking and generation. flag the microcontroller if errors exist during transmission. address checking. ignore the transactions not addressed to the device. send appropriate ack/nak/stall handshakes. token type identification (setup, in, or out). set the appropriate token bit after a valid token is received. place valid received data in the appropriate endpoint fifos. send and update the data toggle bit (data1/0). bit stuffing and unstuffing. firmware is required to handle the rest of the usb interface with the following tasks: coordinate enumeration by decoding usb device requests. fill and empty the fifos. suspend and resume coordination. verify and select data toggle values. table 19-1. usb transceiver configure register (usbxcr) [0x74] [r/w] bit # 7 6 5 4 3 2 1 0 field usb pull-up enable reserved usb force state read/write r/w ? ? ? ? ? ? r/w default 0 0 0 0 00 0 0 bit 7: usb pull-up enable 0 = disable the pull-up resistor on d? 1 = enable the pull-up resistor on d?. this pull-up is to v cc if the phy?s internal voltage regulator is not enabled or to the internally generated 3.3v when vreg is enabled. bit [6:1]: reserved bit 0: usb force state this bit allows the state of the usb io pins d? and d+ to be forced to a state when usb is enabled. 0 = disable usb force state 1 = enable usb force state. allows the d? and d+ pins to be c ontrolled by p1.1 and p1.0 respectively when the usbio is in usb mode. refer to table 14-2 on page 35 for more information. note the usb transceiver has a dedicated 3.3 v regulator for usb si gnalling purposes and to provide for the 1.5 k d? pull-up. unlike the other 3.3 v regulator, this regul ator cannot be controlled or accessed by firmware. when the device is suspended, this regulator is disabled along with the bandgap (which provides the reference voltage to the regulator) and the d? line is pulled up to 5 v through an alternate 6.5 k resistor. during wake up following a suspend, the band gap and the regulator are switched on in any order. under an extremely rare case when the device wakes up following a bus reset condition and the volt- age regulator and the band gap turn on in that particular order, th ere is possibility of a glitch or low pulse occurring on the d? line. the host can misinterpret this as a detach condition. this condition, although rare, is avoided by keeping the bandgap ci r- cuitry enabled during sleep. this is achieved by setting the ?no buzz? bit, bit[5] in the osc_cr0 register. this is an issue on ly if the device is put to sleep during a bus reset condition. [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 59 of 86 21. usb device 21.1 usb device address 21.2 endpoint 0, 1, and 2 count table 21-1. usb device address (usbcr) [0x40] [r/w] bit # 7 6 5 4 3 2 1 0 field usb enable device address[6:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit 7: usb enable this bit must be enabled by firmware before the serial interfac e engine (sie) responds to the usb traffic at the address specif ied in device address [6:0]. when this bit is cleared, the usb tran sceiver enters power down state. user?s firmware must clear this bit before entering sleep mode to save power. 0 = disable usb device address and put the usb transceiver into power down state. 1 = enable usb device address and put the usb transceiver into normal operating mode. bit [6:0]: device address [6:0] these bits must be set by firmware during the usb enumeratio n process (that is, setaddress) to the nonzero address assigned by the usb host. table 21-2. endpoint 0, 1, and 2 count (ep0cnt?ep2cnt) [0x41, 0x43, 0x45] [r/w] bit # 7 6 5 4 3 2 1 0 field data toggle data valid reserved byte count[3:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit 7: data toggle this bit selects the data packet's toggle state. for in transacti ons, firmware must set this bit to select the transmitted data toggle. for out or setup transactions, the hardware sets this bit to the state of the received data toggle bit. 0 = data0 1 = data1 bit 6: data valid this bit is used for out and setup tokens only. this bit is clear ed to ?0? if crc, bitstuff, or pid errors have occurred. this bit does not update for some endpoint mode settings. 0 = data is invalid. if enabled, the endpoint in terrupt occurs even if invalid data is received. 1 = data is valid bit [5:4]: reserved bit [3:0]: byte count bit [3:0] byte count bits indicate the number of data bytes in a transac tion: for in transactions, firmware loads the count with the numb er of bytes to be transmitted to th e host from the endpoint fifo. valid values are 0 to 8 inclusive. for out or setup transactions , the count is updated by hardware to the number of data bytes received, plus 2 for the crc bytes. valid values are 2?10 inclusiv e. for endpoint 0 count register, when the count updates from a setup or out transaction, the count register locks and cannot be written by the cpu. reading the register unlocks it. this prevents firmware from overwriting a st atus update on it. [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 60 of 86 21.3 endpoint 0 mode because both firmware and the sie are allowed to write to the endpoint 0 mode and count registers, the sie provides an interloc king mechanism to prevent accidental overwriting of data. when the sie writes to these r egisters they are locked and the processor cannot write to them unt il after it has read them. wri ting to this register clears the upper four bits regardless of the value written. table 21-3. endpoint 0 mo de (ep0mode) [0x44] [r/w] bit # 7 6 5 4 3 2 1 0 field setup received in received out received ack?d trans mode[3:0] read/write r/c [5] r/c [5] r/c [5] r/c [5] r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit 7: setup received this bit is set by hardware when a valid setup packet is rece ived. it is forced high from the start of the data packet phase of the setup transactions until the end of t he data phase of a control write transfer, and cannot be cleared during this interval. while this bit is set to ?1?, the cpu ca nnot write to the ep0 fifo. this prevents firmware from overwriting an incoming setup transaction before firmware has a chance to read the setup data. this bit is cleared by any nonlocked writes to the register. 0 = no setup received ? 1 = setup received bit 6: in received this bit when set indicates a valid in packet has been received. this bit is updated to ?1? after the host acknowledges an in d ata packet. when clear, it indicates either no in has been received or that the host did not acknowledge the in data by sending ack handshake. this bit is cleared by any nonlocked writes to the register. 0 = no in received ? 1 = in received bit 5: out received this bit when set indicates a valid out packet has been received and acked. this bit is updated to ?1? after the last received packet in an out transaction. when clear, it indicates no out received. this bit is cleared by any nonlocked writes to the register. 0 = no out received ? 1 = out received bit 4: ack?d transaction the ack?d transaction bit is set when the sie engages in a transaction to the register?s endpoint, which completes with a ack packet. this bit is cleared by any nonlocked writes to the register. 1 = the transaction completes with an ack. ? 0 = the transaction does not complete with an ack. bit [3:0]: mode [3:0] the endpoint modes determine how the sie responds to the usb traffic that the host sends to the endpoint. the mode controls how the usb sie responds to traffic, and how the usb sie changes the mode of that endpoint as a result of host packets to the endpoint. note 5. c = clear. this bit is cleared only by the user and cannot be set by firmware. [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 61 of 86 21.4 endpoint 1 and 2 mode table 21-4. endpoint 1 and 2 mode (ep1mode ? ep2mode) [0x45, 0x46] [r/w] bit # 7 6 5 4 3 2 1 0 field stall reserved nak int enable ack?d transaction mode[3:0] read/write r/w r/w r/w r/c (note 4) r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit 7: stall when this bit is set the sie stalls an out packet if the mode bi ts are set to ack-out, and the sie stalls an in packet if the mode bits are set to ack-in. this bit must be clear for all other modes bit 6: reserved bit 5: nak int enable this bit when set causes an endpoint interrupt to be generat ed even when a transfer completes with a nak. unlike encore, encore ii family members do not generate an endpoint in terrupt under these conditions unless this bit is set. 0 = disable interrupt on nak?d transactions ? 1 = enable interrupt on nak?d transaction bit 4: ack?d transaction the ack?d transaction bit is set when the sie engages in a tran saction to the register?s endpo int that completes with an ack packet. this bit is cleared by any writes to the register. 0 = the transaction does not complete with an ack ? 1 = the transaction completes with an ack bit [3:0]: mode [3:0] the endpoint modes determine how the sie responds to usb traffi c that the host sends to the endpoint. the mode controls how the usb sie responds to traffic, and how the usb sie changes the mode of that endpoint as a result of host packets to the endpoint. note when the sie writes to the ep1mode or the ep2mode register, it blocks fi rmware writes to the ep2mode or the ep1mode registers respectively (if both writes occur in the sa me clock cycle). this is becaus e the design empl oys only one common ?update? signal for both ep1mode and ep2mode regist ers. as a result, when sie writes to say ep1mode register, the update signal is set and this prevents firmware writes to ep2 mode register. sie writes to the endpoint mode registers have higher priority than firmware writes. this mode register write block situation can put the endpoints in incorrect modes. firmwa re must read the ep1/2mode registers immediately following a firmware write and rewrite if the value read is incorrect. table 21-5. endpoint 0 data (ep0data) [0x50-0x57] [r/w] bit # 7 6 5 4 3 2 1 0 field endpoint 0 data buffer [7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default unknown unknown unknown unknown unknown unknown unknown unknown the endpoint 0 buffer is comprised of 8 bytes located at address 0x50 to 0x57. table 21-6. endpoint 1 data (ep1data) [0x58-0x5f] [r/w] bit # 7 6 5 4 3 2 1 0 field endpoint 1 data buffer [7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default unknown unknown unknown unknown unknown unknown unknown unknown the endpoint 1 buffer is comprised of 8 bytes located at address 0x58 to 0x5f. [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 62 of 86 the three data buffers are used to hold data for both in and out transactions. each data buffer is 8 bytes long. the reset values of the endpoint data registers are unknown. unlike past encore parts the usb data buffers are onl y accessible in the io space of the processor. 22. usb mode tables 22.1 mode column the 'mode' column contains the mnemonic names given to the modes of the endpoint. the mode of the endpoint is determined by the 4-bit binaries in the 'encoding' column as discussed in the following sections. the status in and status out represent the status in or out stage of the control transfer. 22.2 encoding column the contents of the 'encoding' column represent the mode bits [3:0] of the endpoint mode registers ( table 21-3 on page 60 and table 21-4 on page 61 ). the endpoint modes determine how the sie responds to different tokens that the host sends to the endpoints. for example, if the mode bits [3:0] of the endpoint 0 mode register are set to '0001', which is nak in/out mode, the sie sends an ack handshake in response to setup tokens and nak any in or out tokens. table 21-7. endpoint 2 data (ep2data) [0x60-0x67] [r/w] bit # 7 6 5 4 3 2 1 0 field endpoint 2 data buffer [7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default unknown unknown unknown unknown unknown unknown unknown unknown the endpoint 2 buffer is comprised of 8 bytes located at address 0x60 to 0x67. mode encoding setup in out comments disable 0000 ignore ignore ignore ignore all usb traffic to this endpoint. used by data and control endpoints. nak in/out 0001 accept nak nak nak in and out token. control endpoint only. status out only 0010 accept stall check stall in and ack zero byte out. control endpoint only. stall in/out 0011 accept stall stall stall in and out token. control endpoint only. status in only 0110 accept tx0 byte stall stall out and send zero byte data for in token. con- trol endpoint only. ack out ? status in 1011 accept tx0 byte ack ack the out token or send zero byte data for in token. control endpoint only. ack in ? status out 1111 accept tx count check respond to in data or status out. control endpoint only. nak out 1000 ignore ignore nak send nak handshake to out token. data endpoint only. ack out (stall = 0) 1001 ignore ignore ack this mode is changed by the sie to mode 1000 on is- suance of ack handshake to an out. data endpoint only. ack out (stall = 1) 1001 ignore ignore stall stall the out transfer. nak in 1100 ignore nak ignore send nak handshake for in token. data endpoint only. ack in (stall = 0) 1101 ignore tx count ignore this mode is changed by the sie to mode 1100 after receiving ack handshake to an in data. data endpoint only. ack in (stall = 1) 1101 ignore stall ignore stall the in transfer. data endpoint only. reserved 0101 ignore ignore ignore these modes are not supported by sie. firmware must not use this mode in control and data endpoints. reserved 0111 ignore ignore ignore reserved 1010 ignore ignore ignore reserved 0100 ignore ignore ignore reserved 1110 ignore ignore ignore [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 63 of 86 22.3 setup, in, and out columns depending on the mode specified in the 'encoding' column, the 'setup', 'in', and 'out' columns contain the sie's responses when the endpoint receives setup, in, and out tokens, respectively. a 'check' in the out column means that upon receiving an out token the sie checks to see whether the out is of zero length and has a data toggle (data1/0) of 1. if these conditions are true , the sie responds with an ack. if any of the these conditions is not met, the sie responds with a stall or ignore. a 'tx count' entry in the in column means that the sie transmits the num ber of bytes specified in the byte count bit [3:0] of t he endpoint count register ( ta b l e 21-2 ) in response to any in token. 23. details of mode fo r differing traffic conditions control endpoint sie bus event sie ep0 mode register ep0 count register ep0 interrupt comments mode token count dval d0/1 response s i o a mode dtog dval count fifo disabled 0000 x x x x ignore all stall_in_out 0011 setup >10 x x junk ignore 0011 setup <=10 invalid x junk ignore 0011 setup <=10 valid x ack 1 1 0001 update 1 update data yes ack setup 0011 in x x x stall stall in 0011 out >10 x x ignore 0011 out <=10 invalid x ignore 0011 out <=10 valid x stall stall out nak_in_out 0001 setup >10 x x junk ignore 0001 setup <=10 invalid x junk ignore 0001 setup <=10 valid x ack 1 1 0001 update 1 update data yes ack setup 0001 in x x x nak nak in 0001 out >10 x x ignore 0001 out <=10 invalid x ignore 0001 out <=10 valid x nak nak out ack_in_status_out 1111 setup >10 x x junk ignore 1111 setup <=10 invalid x junk ignore 1111 setup <=10 valid x ack 1 1 0001 update 1 update data yes ack setup 1111 in x x x tx host not ack'd 1111 in x x x tx 1 1 0001 yes host ack'd 1111 out >10 x x ignore 1111 out <=10 invalid x ignore 1111 out <=10, <>2 valid x stall 0011 yes bad status 1111 out 2 valid 0 stall 0011 yes bad status 1111 out 2 valid 1 ack 1 1 0010 1 1 2 yes good status status_out 0010 setup >10 x x junk ignore 0010 setup <=10 invalid x junk ignore 0010 setup <=10 valid x ack 1 1 0001 update 1 update data yes ack setup 0010 in x x x stall 0011 yes stall in 0010 out >10 x x ignore 0010 out <=10 invalid x ignore [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 64 of 86 0010 out <=10, <>2 valid x stall 0011 yes bad status 0010 out 2 valid 0 stall 0011 yes bad status 0010 out 2 valid 1 ack 1 1 1 1 2 yes good status ack_out_status_in 1011 setup >10 x x junk ignore 1011 setup <=10 invalid x junk ignore 1011 setup <=10 valid x ack 1 1 0001 update 1 update data yes ack setup 1011 in x x x tx 0 host not ack'd 1011 in x x x tx 0 1 1 0011 yes host ack'd 1011 out >10 x x junk ignore 1011 out <=10 invalid x junk ignore 1011 out <=10 valid x ack 1 1 0001 update 1 update data yes good out status_in 0110 setup >10 x x junk ignore 0110 setup <=10 invalid x junk ignore 0110 setup <=10 valid x ack 1 1 0001 update 1 update data yes ack setup 0110 in x x x tx 0 host not ack'd 0110 in x x x tx 0 1 1 0011 yes host ack'd 0110 out >10 x x ignore 0110 out <=10 invalid x ignore 0110 out <=10 valid x stall 0011 yes stall out data out endpoints ack out (stall bit = 0) 1001 in x x x ignore 1001 out >max x x junk ignore 1001 out <=max invalid invalid junk ignore 1001 out <=max valid valid ack 1 1000 update 1 update data yes ack out ack out (stall bit = 1) 1001 in x x x ignore 1001 out >max x x ignore 1001 out <=max invalid invalid ignore 1001 out <=max valid valid stall stall out nak out 1000 in x x x ignore 1000 out >max x x ignore 1000 out <=max invalid invalid ignore 1000 out <=max valid valid nak if enabled nak out data in endpoints ack in (stall bit = 0) 1101 out x x x ignore 1101 in x x x host not ack'd 1101 in x x x tx 1 1100 yes host ack'd ack in (stall bit = 1) 1101 out x x x ignore 23. details of mode fo r differing traffic conditions (continued) control endpoint sie bus event sie ep0 mode register ep0 count register ep0 interrupt comments mode token count dval d0/1 response s i o a mode dtog dval count fifo [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 65 of 86 1101 in x x x stall stall in nak in 1100 out x x x ignore 1100 in x x x nak if enabled nak in 23. details of mode for differing traffic conditions (continued) control endpoint sie bus event sie ep0 mode register ep0 count register ep0 interrupt comments mode token count dval d0/1 response s i o a mode dtog dval count fifo 24. register summary the xio bit in the cpu flags register must be set to acce ss the extended register space for all registers above 0xff. addr name 7 6 5 4 3 2 1 0 r/w default 00 p0data p0.7 p0.6/tio1 p0.5/tio0 p0.4/int2 p0.3/int1 p0.2/int0 p0.1/clk - out p0.0/clki n bbbbbbbb 00000000 01 p1data p1.7 p1.6/smi so p1.5/smo si p1.4/sclk p1.3/ssel p1.2/vreg p1.1/d? p1.0/d+ bbbbbbbb 00000000 02 p2data res p2.1?p2.0 bbbbbbbb 00000000 03 p3data res p3.1?p3.0 bbbbbbbb 00000000 04 p4data res res ----bbbb 00000000 05 p00cr reserved int enable int act low ttl thresh reserved open drain pull-up enable output enable -bbbbbbb 00000000 06 p01cr clk output int enable int act low ttl thresh reserved open drain pull-up enable output enable bbbbbbbb 00000000 07?09 p02cr? p04cr reserved reserved int act low ttl thresh reserved open drain pull-up enable output enable --bbbbbb 00000000 0a?0b p05cr? p06cr tio output int enable int act low ttl thresh reserved open drain pull-up enable output enable bbbbbbbb 00000000 0c p07cr reserved int enable int act low ttl thresh reserved open drain pull-up enable output enable -bbbbbbb 00000000 0d p10cr reserved int enable int act low reserved ps/2 pull-up enable output enable -bb---bb 00000000 0e p11cr reserved int enable int act low reserved open drain reserved output enable -bb--b-b 00000000 0f p12cr clk output int enable int act low ttl thresh reserved open drain pull-up enable output enable bbbbbbbb 00000000 10 p13cr reserved int enable int act low 3.3 v drive high sink open drain pull-up enable output enable -bbbbbbb 00000000 11?13 p14cr? p16cr spi use int enable int act low 3.3 v drive high sink open drain pull-up enable output enable bbbbbbbb 00000000 14 p17cr reserved int enable int act low ttl thresh high sink open drain pull-up enable output enable -bbbbbbb 00000000 15 p2cr reserved int enable int act low ttl thresh reserved open drain pull-up enable output enable -bbbbbbb 00000000 16 p3cr reserved int enable int act low ttl thresh reserved open drain pull-up enable output enable -bbbbbbb 00000000 20 frtmrl free running timer [7:0] bbbbbbbb 00000000 21 frtmrh free running timer [15:8] bbbbbbbb 00000000 22 tcap0r capture 0 rising [7:0] bbbbbbbb 00000000 23 tcap1r capture 1 rising [7:0] bbbbbbbb 00000000 24 tcap0f capture 0 falling [7:0] bbbbbbbb 00000000 25 tcap1f capture 1 falling [7:0] bbbbbbbb 00000000 26 pitmrl prog interval timer [7:0] bbbbbbbb 00000000 27 pitmrh reserved prog interval timer [11:8] ----bbbb 00000000 28 pirl prog interval [7:0] bbbbbbbb 00000000 29 pirh reserved prog interval [11:8] ----bbbb 00000000 [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 66 of 86 2a tmrcr first edge hold 8-bit capture prescale cap0 16bit enable reserved bbbbb--- 00000000 2b tcapinte reserved cap1 fall active cap1 rise active cap0 fall active cap0 rise active ----bbbb 00000000 2c tcapints reserved cap1 fall active cap1 rise active cap0 fall active cap0 rise active ----bbbb 00000000 30 cpuclkcr reserved usb clk/2 disable usb clk select reserved cpu clk select -bb----b 00010000 31 itmrclkcr tcapclk divider tcapclk select itmrclk divider itmrclk select bbbbbbbb 1000 1111 32 clkiocr reserved reserved clkout select ---bbbbb 00000000 34 iosctr foffset[2:0] gain[4:0] bbbbbbbb 000ddddd 36 lposctr 32 khz low power reserved 32 khz bias trim [1:0] 32 khz freq trim [3:0] b-bbbbbb dddddddd 39 osclckcr reserved fine tune only usb osclock disable ------bb 00000000 3c spidata spidata[7:0] bbbbbbbb 00000000 3d spicr swap lsb first comm mode cpol cpha sclk select bbbbbbbb 00000000 40 usbcr usb enable device address[6:0] bbbbbbbb 00000000 41 ep0cnt data to g g l e data valid reserved byte count[3:0] bbbbbbbb 00000000 42 ep1cnt data to g g l e data valid reserved byte count[3:0] bbbbbbbb 00000000 43 ep2cnt data to g g l e data valid reserved byte count[3:0] bbbbbbbb 00000000 44 ep0mode setup rcv?d in rcv?d out rcv?d ack?d trans mode[3:0] ccccbbbb 00000000 45 ep1mode stall reserved nak int enable ack?d trans mode[3:0] b-bcbbbb 00000000 46 ep2mode stall reserved nak int enable ack?d trans mode[3:0] b-bcbbbb 00000000 50?57 ep0data endpoint 0 data buffer [7:0] bbbbbbbb ???????? 58?5f ep1data endpoint 1 data buffer [7:0] bbbbbbbb ???????? 60?67 ep2data endpoint 2 data buffer [7:0] bbbbbbbb ???????? 73 vregcr reserved keep alive vreg enable ------bb 00000000 74 usbxcr usb pull-up enable reserved usb force state b------b 00000000 da int_clr0 gpio port 1 sleep timer int1 gpio port 0 spi receive spi transmit int0 por/lvd bbbbbbbb 00000000 db int_clr1 tcap0 prog interval timer 1-ms timer usb active usb reset usb ep2 usb ep1 usb ep0 bbbbbbbb 00000000 dc int_clr2 reserved reserved gpio port 3 gpio port 2 ps/2 data low int2 16-bit counter wrap tcap1 -bbbbbbb 00000000 de int_msk3 enswint reserved b------- 00000000 df int_msk2 reserved reserved gpio port 3 int enable gpio port 2 int enable ps/2 data low int enable int2 int enable 16-bit counter wrap int enable tcap1 int enable -bbbbbbb 00000000 e1 int_msk1 tcap0 int enable prog interval timer int enable 1-ms timer int enable usb active int enable usb reset int enable usb ep2 int enable usb ep1 int enable usb ep0 int enable bbbbbbbb 00000000 24. register summary (continued) the xio bit in the cpu flags register must be set to acce ss the extended register space for all registers above 0xff. addr name 7 6 5 4 3 2 1 0 r/w default [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 67 of 86 legend ? in the r/w column, ? b = both read and write ? r = read only ? w = write only ? c = read/clear ? ? = unknown ? d = calibration value. must not change during normal use. e0 int_msk0 gpio port 1 int enable sleep timer int enable int1 int enable gpio port 0 int enable spi receive int enable spi transmit int enable int0 int enable por/lvd int enable bbbbbbbb 00000000 e2 int_vc pending interrupt [7:0] bbbbbbbb 00000000 e3 reswdt reset watchdog timer [7:0] wwwwwwww 00000000 -- cpu_a temporary register t1 [7:0] -------- 00000000 -- cpu_x x[7:0] -------- 00000000 -- cpu_pcl program counter [7:0] -------- 00000000 -- cpu_pch program counter [15:8] -------- 00000000 -- cpu_sp stack pointer [7:0] -------- 00000000 - cpu_f reserved xoi super carry zero global ie ---brwww 00000010 ff cpu_scr gies reserved wdrs pors sleep reserved reserved stop r-ccb--b 00010000 1e0 osc_cr0 reserved no buzz sleep timer [1:0] cpu speed [2:0] --bbbbbb 00000000 1e3 lvdcr reserved porlev[1:0] reserved vm[2:0] --bb-bbbb 00000000 1eb eco_tr sleep duty cycle [1:0] reserved bb------ 00000000 1e4 vltcmp reserved lvd ppor ------rr 00000000 24. register summary (continued) the xio bit in the cpu flags register must be set to acce ss the extended register space for all registers above 0xff. addr name 7 6 5 4 3 2 1 0 r/w default [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 68 of 86 25. voltage vs cpu fr equency characteristics figure 25-1. voltage vs cpu frequency characteristics running the cpu at 24 mhz requires a minimum voltage of 4.75 v. this applies to any cpu speed above 12 mhz, so using an external clock between 12?24 mhz must also adhere to this requirement. operating the cp u at 24mhz when the supply voltage is below 4.75 v can cause undesired behavior and must be avoided. many encore ii applications use usb vbus 5 v as the power source for the device. accordin g to the usb specification, voltage can be less than 4.75 v on vbus (if the usb port is a low power port the voltage can be between 4.4 v and 5.25 v). even for externally powered 5 v applications, developers must consider that on power up and power down voltage is less than 4.75v for some time. firmware must be implemented properly to prevent undesired behavior. use of 24 mhz requires the use of the high por trip point of approximately 4.55?4.65 v (register lvdcr 0x1e3, porlev[1:0] = 10b). this setting is sufficient to protect the device from problems due to oper ating at low voltage with cpu speeds above 12 mhz. this must be set before setting the cpu speed to greater than 12 mhz. for devices with slow power ramps, changing the por threshold to the high level may result in one or more resets of the device as power ramps through the chip default por set point of approximately 2.6 v up through the high por set point. if multiple resets are undesirable for slow power ramps, then firmware must do the following: set the low voltage detection circuit (register lvdcr 0x1e3, vm[2:0]) for one of the set points above the por (vm[2:0] = 110 b ~4.73 v or 111b ~4.82 v). monitor the lvd until voltage is above the trip point (register vltcmp 0x1e4, bit 1 is clear). debounce the indication to ensure that voltage is above the set point for possible noisy supplies. set the por to the high set point. shift cpu speed to 24 mhz. if the supply voltage dips below 4.75 v and the application can tolerate running at a cpu speed of 12 mhz, then application firmware may also implement the following to minimize the chance of a reset event due to a voltage transient: set the lvd for one of the desired high setting (~4.73 v or ~4.82 v). enable the lvd interrupt. in the lvd isr, reduce cpu speed to 12 mhz and shift the por to a lower threshold. firmware can monitor for vltcmp to clear within the normal application main loop. debounce the indication to ensure voltage is above the set point. shift the por to the high set point. shift the cpu to 24 mhz. 93 khz 12 mhz 24 mhz cpu frequency vdd (volts) 4.00 4.75 5.50 v a l i d o p er a ti n g r e g io n note 6. in master mode, first bit is available 0.5 spiclk cyc le before master clock edge available on the sclk pin. [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 69 of 86 26. absolute maximum ratings exceeding maximum ratings may s horten the useful life of the device. user guidelines are not tested. storage temperature ................................. ?40 c to +90 c ambient temperature with power applied... ?0 c to +70 c supply voltage on v cc relative to v ss ........ ?0.5 v to +7.0 v dc input voltage .............................. ?0.5 v to + v cc + 0.5 v dc voltage applied to outputs in ? high-z state..................................... ?0.5 v to + v cc + 0.5 v maximum total sink current into port 0 ? and port 1 pins ............................................................ 70 ma maximum total source output current into gpio pins30 ma maximum on-chip po wer dissipation ? on any gpio pin......................................................... 50 mw power dissipation .................................................... 300 mw static discharge voltage ............................................ 2200 v latch up current ..................................................... 200 ma 27. dc characteristics parameter description conditions min typical max unit general v cc1 operating voltage no usb activity, cpu speed < 12 mhz 4.0 ? 5.5 v v cc2 operating voltage usb activity, cpu speed < 12 mhz 4.35 ? 5.25 v v cc3 operating voltage flash programming 4.0 ? 5.5 v v cc4 operating voltage no usb activity, cpu speed is between 12 mhz and 24 mhz 4.75 ? 5.5 v t fp operating temp flash programming 0 ? 70 c i cc1 v cc operating supply current v cc = 5.25 v, no gpio loading, ? 24 mhz ? ? 40 ma i cc2 v cc operating supply current v cc = 5.0 v, no gpio loading, 6 mhz ? 10 ma i sb1 standby current internal and external oscillators, bandgap, flash, cpu clock, timer clock, usb clock all disabled ? ? 10 ? a low voltage detect v lvd low-voltage detect trip voltage (8 programmable trip points) ? 2.681 ? 4.872 v 3.3v regulator i vreg max regulator output current 4.35 v < v cc < 5.5 v ? ? 125 ma i ka keep alive current when regulator is disabled with ?keep alive? enable ? ? 20 ? a v ka keep alive voltage keep alive bit set in vregcr 2.35 ? 3.8 v v reg1 v reg output voltage v cc > 4.35 v, 0 < temp < 40 c, ? 25 ma < i vreg < 125 ma (3.3v 8%) t = 0 to 70 c 3.0 ? 3.6 v v reg2 v reg output voltage v cc > 4.35 v, 0 < temp < 40 c, ? 1 ma < i vreg < 25 ma (3.3v 4%) t = 0 to 40 c 3.15 ? 3.45 v c load capacitive load on vreg pin ? 1 ? 2 ? f ln reg line regulation ? ? ? 1 %/v ld reg load regulation ? ? ? 0.04 %/ma usb interface v on static output high 15 k 5% ohm to v ss 2.8 ? 3.6 v v off static output low r up is enabled ? ? 0.3 v notes 7. available only in cy7c638xx p1.3, p1.4, p1.5, p1.6, p1.7. 8. except for pins p1.0 and p1.1 in the gpio mode. 9. except for pins p1.0 and p1.1. [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 70 of 86 v di differential input sensitivity ? 0.2 ? ? v v cm differential input common mode range ? 0.8 ? 2.5 v v se single ended receiver threshold ? 0.8 ? 2 v c in transceiver capacitance ? ? ? 20 pf i io hi-z state data line leakage 0v < v in < 3.3 v ?10 ? 10 ? a ps/2 interface v olp static output low sdata or sclk pins ? ? 0.4 v r ps2 internal ps/2 pull-up resistance sdata, sclk pins, ps/2 enabled 3 ? 7 k ? general purpose io interface r up pull-up resistance 4 ? 12 k ? v icr input threshold voltage low, cmos mode [ 8 ] low to high edge 40% ? 65% v cc v icf input threshold voltage low, cmos mode [ 8 ] high to low edge 30% ? 55% v cc v hc input hysteresis voltage, cmos mode [ 8 ] high to low edge 3% ? 10% v cc v ilttl input low voltage, ttl mode [9] i/o pin supply = 4.0?5.5 v ? 0.8 v v ihttl input high voltage, ttl mode [9] i/o pin supply = 4.0?5.5 v 2.0 ? v v ol1 output low voltage, high drive [7] i ol1 = 50 ma ? ? 0.8 v v ol2 output low voltage, high drive [7] i ol1 = 25 ma ? ? 0.4 v v ol3 output low voltage, low drive [8] i ol2 = 8 ma ? ? 0.4 v v oh output high voltage [8] i oh = 2 ma v cc ?0.5 ? ? v c load maximum load capacitance [9] ? ? ? 50 pf 27. dc characteristics (continued) parameter description conditions min typical max unit general 28. ac characteristics parameter description conditions min typical max unit clock t eclkdc external clock duty cycle ? 45 ? 55 % t eclk1 external clock frequency external clock is the source of the cpuclk 0.187 ? 24 mhz t eclk2 external clock frequency external clock is not the source of the cpuclk 0 ? 24 mhz f imo1 internal main oscillator frequency no usb present 22.8 ? 25.2 mhz f imo2 internal main oscillator frequency with usb present 23.64 ? 24.3 mhz f ilo1 internal low power oscillator normal mode 29.44 ? 37.12 khz f ilo2 internal low power oscillator low power mode 35.84 ? 47.36 khz 3.3 v regulator v orip output ripple voltage 10 hz to 100 mhz at cload = 1 ? f ? ? 200 mv p-p note 10. in master mode, first bit is available 0.5 spiclk cycle before master clock edge available on the sclk pin. [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 71 of 86 usb driver t r1 transition rise time c load = 200 pf 75 ? ? ns t r2 transition rise time c load = 600 pf ? 300 ns t f1 transition fall time c load = 200 pf 75 ? ns t f2 transition fall time c load = 600 pf ? 300 ns t r rise/fall time matching ? 80 ? 125 % v crs output signal crossover voltage ? 1.3 ? 2.0 v usb data timing t drate low speed data rate average bit rate (1.5 mbps 1.5%) 1.4775 ? 1.5225 mbps t djr1 receiver data jitter tolerance to next transition ?75 ? 75 ns t djr2 receiver data jitter tolerance to pair transition ?45 ? 45 ns t deop differential to eop transition skew ? ?40 ? 100 ns t eopr1 eop width at receiver rejects as eop ? 330 ns t eopr2 eop width at receiver accept as eop 675 ? ns t eopt source eop width ? 1.25 ? 1.5 ? s t udj1 differential driver jitter to next transition ?95 ? 95 ns t udj2 differential driver jitter to pair transition ?95 ? 95 ns t lst width of se0 during diff. transition ? ? ? 210 ns non-usb mode driver characteristics t fps2 sdata/sck transition fall time ? 50 ? 300 ns gpio timing t r_gpio output rise time [8] measured between 10 and 90% vdd/vreg with 50 pf load ? ? 50 ns t f_gpio output fall time [8] measured between 10 and 90% vdd/vreg with 50 pf load ? ? 15 ns spi timing t smck spi master clock rate f cpuclk /6 ? ? 2 mhz t ssck spi slave clock rate ? ? ? 2.2 mhz t sckh spi clock high time high for cpol = 0, low for cpol = 1 125 ? ? ns t sckl spi clock low time low for cpol = 0, high for cpol = 1 125 ? ? ns t mdo master data output time [10] sck to data valid ?25 ? 50 ns t mdo1 master data output time, ? first bit with cpha = 0 time before leading sck edge 100 ? ? ns t msu master input data setup time ? 50 ? ? ns t mhd master input data hold time ? 50 ? ? ns t ssu slave input data setup time ? 50 ? ? ns t shd slave input data hold time ? 50 ? ? ns t sdo slave data output time sck to data valid ? 100 ns t sdo1 slave data output time, ? first bit with cpha = 0 time after ss low to data valid ? ? 100 ns t sss slave select setup time before first sck edge 150 ? ? ns t ssh slave select hold time after last sck edge 150 ? ? ns 28. ac characteristics (continued) parameter description conditions min typical max unit [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 72 of 86 1 figure 28-2. gpio timing diagram figure 28-1. clock timing figure 28-3. usb data signal timing clock t cyc t cl t ch 10% t r_gpio t f_gpio gpio pin output voltage 90% 90% 10% 90% 10% d ? d ? t r t f v crs v oh v ol figure 28-4. receiver jitter tolerance differential data lines paired transitions n * t period + t jr2 t period consecutive transitions n * t period + t jr1 t jr t jr1 t jr2 [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 73 of 86 figure 28-5. differential to eo p transition skew and eop width t period differential data lines crossover point crossover point extended source eop width: t eopt receiver eop width: t eopr1 , t eopr2 diff. data to se0 skew n * t period + t deop figure 28-6. differential data jitter t period differential data lines crossover points paired transitions n * t period + t xjr2 consecutive transitions n * t period + t xjr1 [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 74 of 86 figure 28-7. spi master timing, cpha = 1 msb t msu lsb t mhd t sckh t mdo ss sck (cpol=0) sck (cpol=1) mosi miso (ss is under firmware control in spi master mode) t sckl msb lsb figure 28-8. spi slave timing, cpha = 1 msb t ssu lsb t shd t sckh t sdo ss sck (cpol=0) sck (cpol=1) mosi miso t sckl t sss t ssh msb lsb [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 75 of 86 figure 28-9. spi master timing, cpha = 0 figure 28-10. spi slave timing, cpha = 0 msb t msu lsb t mhd t sckh t mdo1 ss sck (cpol=0) sck (cpol=1) mosi miso (ss is under firmware control in spi master mode) t sckl t mdo lsb msb msb t ssu lsb t shd t sckh t sdo1 ss sck (cpol=0) sck (cpol=1) mosi miso t sckl t sdo lsb msb t sss t ssh [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 76 of 86 29. ordering information ordering code flash size ram size package type cy7c63310-sxc 3k 128 16-soic cy7c63801-sxc 4k 256 16-soic cy7c63803-sxc 8k 256 16-soic cy7c63803-sxct 8k 256 16-soic, tape and reel cy7c63813-pxc 8k 256 18-pdip cy7c63813-sxc 8k 256 18-soic CY7C63823-QXC 8k 256 24-qsop cy7c63823-sxc 8k 256 24-soic cy7c63823-sxct 8k 256 24-soic, tape and reel cy7c63803-lqxc 8k 256 24-qfn sawn cy7c63823-xc 8k 256 die form cy7c63833-ltxc 8k 256 32-qfn sawn cy7c63833-ltxct 8k 256 32-qfn sawn, tape and reel 29.1 ordering code definitions 30. package handling some ic packages require baking before they are soldered onto a pc b to remove moisture that may have been absorbed after leavin g the factory. a label on the packaging has de tails about actual bake temperature and the minimum bake time to remove this moistu re. the maximum bake time is the aggregate time that the parts are exposed to the bake temperature. exceeding this exposure time ma y degrade device reliability. parameter description min typical max unit t baketemp bake temperature ? 125 see package label c t baketime bake time see package label ? 72 hours ? temperature grade: c = commercial, i = industrial pb-free package type ? family technology: cmos ? marketing code: 7 = sram company id: cy = cypress 7 cy c xxxxx xx x ct [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 77 of 86 31. package diagrams figure 31-1. 16-pin (300-mil) molded dip p1 figure 31-2. 16-pin (150-mil) soic s16.15 51-85009 *b 51-85068 *c [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 78 of 86 figure 31-3. 18-pin (300-mil) molded dip p3 figure 31-4. 18-pin (300-mil) molded soic s3 51-85010 *c 51-85023 *c [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 79 of 86 figure 31-5. 24-pin (300-mil) soic s13 figure 31-6. 24-pin qsop o241 s 51-85025 *d 51-85055 *c [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 80 of 86 figure 31-7. 24-pin qfn 4x4x0.55 mm lq24 a 2.65x2.65x epad (sawn) figure 31-8. 32-pin qfn package 001-13937 *c 51-85188 *d [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 81 of 86 figure 31-9. 32-pin sawn qfn package 001-30999 *c [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 82 of 86 32. acronyms 33. document conventions units of measure acronym description cmos complementary metal oxide semiconductor ce chip enable i/o input/output oe output enable sram static random access memory tsop thin small outline package we write enable symbol unit of measure ns nano seconds v volts a micro amperes ma milli amperes pf pico farad c degree celsius w watts [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 83 of 86 34. document history page document title: cy7c63310, cy7c638xx encore ? ii low speed usb peripheral controller document number: 38-08035 rev. ecn no. orig. of change submission date description of change ** 131323 xgr 12/11/03 new data sheet *a 221881 kku see ecn added register descriptions and package information, changed from advance information to preliminary *b 271232 bon see ecn reformatted. updated with the latest information *c 299179 bon see ecn corrected 24-pdip pinout typo in table 5-2 on page 7 added table 10-1 on page 22 . updated table 9-5 on page 17 , table 10-3 on page 23 , table 13-1 on page 32 , table 17-1 on page 53 , table 17-3 on page 53 , table 17-5 on page 54 . and table 15-2 on page 42 . added various updates to the gpio section ( general purpose i/o (gpio) ports on page 34 ) corrected table 15-4 on page 43 . corrected figure 28-7 on page 74 and figure 28-8 on page 74 . added the 16-pin pdip package diagram (section package diagrams on page 77 ) *d 322053 tvr bon see ecn introduction on page 4 : removed low-voltage reset in last paragraph. there is no lvr, only lvd (low voltage detect). explained more about lvd and por. changed capture pins from p0.0,p0.1 to p0.5,p0.6. table 6-1 on page 8 : changed table heading (removed mnemonics and made as register names). table 9-5 on page 17 : included #of rows for different flash sizes. clock architecture description on page 22 : changed cpuclk selectable options from n=0- 5,7,8 to n=0-5,7. clocking on page 20 : changed itmrclk division to 1,2,3,4. updated the sources to itmrclk, tcapclks. mentioned p17 is ttl enabled perma - nently. corrected frt, pit data wr ite order. updated intclr, intmsk registers in the register table also. dc characteristics on page 69 : changed lvr to lvd included max min programmable trip points based on char data. updated the 50ma sink pins on 638xx, 63903. keep-alive voltage mentioned corresponding to keep-alive current of 20ua. included notes regarding vol,voh on p1.0,p1.1 and tmdo spec. ac characteristics on page 70 : t mdo1 , t sdo1 in description column changed phase to 0. pinouts on page 5 : removed the vreg from the cy7c63310 and cy7c63801 removed sclk and sdata. created a separate pinout diagram for the cy7c63813. added the gpio block diagram ( figure 14-1 on page 37 ) table 10-4 on page 24 : changed the sleep timer clock unit from 32 khz count to hz. table 21-1 on page 59 : added more descriptions to the register. *e 341277 bha see ecn corrected v ih ttl value in dc characteristics on page 69 . updated v il ttl value. added footnote to pin description table for d+/d? pins. added typical values to low voltage detect table. corrected pin label on 16-pin pdip package. corrected minor typos. *f 408017 tyj see ecn table 5-2 on page 7 : corrected pin assignment for the 24-pin qsop package - gpio port 3 new assignments: pin 19 assigned to p3.0 and pin 20 to p3.1 table 17-6 on page 55 : int_mask1 changed to 0xe1 table 17-7 on page 56 : int_mask0 changed to 0xe0 register summary on page 65 : register summary, address e0 assigned to int_mask0 and address e1 assigned to int_mask1 [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 84 of 86 *g 424790 tyj see ecn minor text changes to make document more readable removed cy7c639xx removed cy7c639xx from ordering information on page 76 added text concerning current draw for p0.0 and p0.1 in table 5-2 on page 7 corrected figure 9-2 on page 16 to represent single stack added comment about availability of 3.3v io on p1.3-p1.6 i table 5-2 on page 7 added information on flash endurance and data retention to section flash on page 15 added block diagrams and timing diagrams added cy7c638xx die form diagrams, pad assignment tables and ordering information keyboard references removed cy7c63923-xc die diagram removed, remo ved references to the 639xx parts updated part numbers in the header *h 491711 tyj see ecn minor text changes 32-qfn part added removed 638xx die diagram and die form pad assignment removed gpio port 4 configuration details corrected gpio characteristics of p0.0 and p0.1 to p1.0 and p1.1 respectively *i 504691 tyj see ecn minor text changes removed all residual references to external crystal oscillator and gpio4 documented the dedicat ed 3.3v regulator for usb transceiver documented bandgap/voltage regulator behavior on wake up voltage regulator line/load regulation documented usb active and ps2 data low interrupt trigger conditions documented. gpio capacitance and timing diagram included method to clear capture interrupt status bit discussed sleep and wake up sequence documented. ep1mode/ep2mode regi ster issue discussed. 34. document history page (continued) document title: cy7c63310, cy7c638xx encore ? ii low speed usb peripheral controller document number: 38-08035 rev. ecn no. orig. of change submission date description of change [+] feedback cy7c63310, cy7c638xx document 38-08035 rev. *m page 85 of 86 *j 2147747 vgt/aesa 05/20/2008 tid number entered on page 1. also changed the sentence ?high current drive on gpio pins? to ?2ma source current on all gpio pins?. point 26.0, dc characteristics on page 69 , changed the min. and max. voltages of vcc3 (line 3) to 4.0 and 5.5 respectively. point 19.0, title modified to ?regulat or output?, instead of ?usb regulator output?. added a point # 3 under point 17.3. changed the storage temperature to ?-40c to 90c? in point # 25.0 ( absolute maximum ratings on page 69 ). added the die form after the end of page 4. in line 3, under ?bit 2: p1.2/vreg? of table 14-2 on page 35 , the changes made were ?cy7c63310/cy7c638xx? instead of ?cy7c63813. in line 1, under ?bit 6: usb clk/2 disable? of table 10-3 on page 23 , entered the word ?clock? instead of ?crystal oscillator?. entered the word ?reserved? and left its corresponding fields blank in the sub-table under ?bit[2:0]: vm[2:0]? of table 13-1 on page 32 . under ?bit [7:6]: sleep duty cycle[ 1:0]?, made the following changes: 0 0 = 1/128 periods of the internal 32 khz low speed oscillator. 0 1 = 1/512 periods of the internal 32 khz low speed oscillator. 1 0 = 1/32 periods of the internal 32 khz low speed oscillator. 1 1 = 1/8 periods of the internal 32 khz low speed oscillator. in table 17-2 on page 53 , in line 4, deleted ?57?, and made the word ?and? to lower case. added 32-pin sawn qfn pin diagram, package diagram, and ordering information. removed references to 3v for the 32 kh z oscillator in section 10. clocking. added information on srom table read - section 9.6. updated section 12.3 low-power in sl eep mode - included set p10cr[1] - during non-usb mode operations. added section 25 - voltage vs cpu frequency char. p1data register information updated. vreg can operate independent of usb connection. included imo and ilo characteristics in the ac char section. updated to data sheet template *e. *k 2620679 cmcc/pyrs 12/12/08 added package handling information *l 2964259 ajha 06/29/10 added partnumber cy7c63803-lqxc to t he ordering information table and added package diagram (spec 001-13937) removed inactive parts from ordering information table. cy7c63310-pxc cy7c63801-pxc cy7c63833-lfxc updated package diagrams. *m 3074654 nxz 10/29/10 added ordering code definition, ac ronyms, and document conventions. 34. document history page (continued) document title: cy7c63310, cy7c638xx encore ? ii low speed usb peripheral controller document number: 38-08035 rev. ecn no. orig. of change submission date description of change [+] feedback document 38-08035 rev. *m revised october 29, 2010 page 86 of 86 psoc designer? is a trademark and psoc? and capsense? are registered trademarks of cypress semiconductor corporation. all produ cts and company names mentioned in this document may be the trademarks of their respective holders. cy7c63310 cy7c638xx ? cypress semiconductor corporation, 2003-2010. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. 35. sales, solutions , and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/ go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/ image psoc cypress.com/go/psoc touch sensing cypress.com/go/ touch usb controllers cypress.com/go/ usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback |
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